Dana Point, CA, USA 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA.
IEEE Computer Society 2011
Last update Thu May 23 18:06:28 2013
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- Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir:
Understanding customer returns from a test perspective.
- Mohammad Hossein Neishaburi, Zeljko Zilic:
A distributed AXI-based platform for post-silicon validation.
- Kanad Basu, Prabhat Mishra:
Efficient trace data compression using statically selected dictionary.
- Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.
- Shreepad Panth, Sung Kyu Lim:
Scan chain and power delivery network synthesis for pre-bond test of 3D ICs.
- Eshan Singh:
Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs.
- Saghir Shaikh:
Test and characterization of high-speed circuits.
- Samah Mohamed Saeed, Ozgur Sinanoglu:
Expedited response compaction for scan power reduction.
- Rajamani Sethuram, Karim Arabi, Mohamed H. Abu-Rahma:
Leakage power profiling and leakage power reduction using DFT hardware.
- Zhongwei Jiang, Zheng Wang, Jing Wang, D. M. H. Walker:
Levelized low cost delay test compaction considering IR-drop induced power supply noise.
- Aritra Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee:
Automatic test stimulus generation for accurate diagnosis of RF systems using transient response signatures.
- Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients.
- Takushi Hashida, Yuuki Araga, Makoto Nagata:
A diagnosis testbench of analog IP cores against on-chip environmental disturbances.
- Ke Peng, Fang Bao, Geoff Shofner, LeRoy Winemberg, Mohammad Tehranipoor:
Case Study: Efficient SDD test generation for very large integrated circuits.
- Irith Pomeranz:
Static test compaction for delay fault test sets consisting of broadside and skewed-load tests.
- Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham:
Efficient and product-representative timing model validation.
- Yasuo Sato:
Special session: Multifaceted approaches for field reliability.
- Mike Laisne:
Advanced methods for leveraging new test standards.
- Siddharth Garg, Diana Marculescu:
Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutions.
- Kurt Rosenfeld, Ramesh Karri:
Security-aware SoC test access mechanisms.
- Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri:
Design and analysis of ring oscillator based Design-for-Trust technique.
- Suriyaprakash Natarajan, Arani Sinha:
The buck stops with wafer test: Dream or reality?
- Kee Sup Kim, Rob Roy:
Apprentice - VTS edition: Season 4.
- Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg:
Special session 5B: Panel How much toggle activity should we be testing with?
- Amitava Majumdar, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou:
A Novel mechanism for speed characterization during delay test.
- Seongmoon Wang:
An efficient method to screen resistive opens under presence of process variation.
- Irith Pomeranz:
On clustering of undetectable transition faults in standard-scan circuits.
- Rudrajit Datta, Nur A. Touba:
Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories.
- Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme:
Programmable extended SEC-DED codes for memory errors.
- Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu:
Training-based forming process for RRAM yield improvement.
- Arani Sinha, Suriyaprakash Natarajan:
The bang for the buck with resiliency: Yield or field?
- Prakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal:
Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation.
- Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty:
Power-safe test application using an effective gating approach considering current limits.
- Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor:
Power-aware test generation with guaranteed launch safety for at-speed scan testing.
- Wing Chiu Tam, Ronald D. Blanton:
SLIDER: A fast and accurate defect simulation framework.
- Ender Yilmaz, Anne Meixner, Sule Ozev:
An industrial case study of analog fault modeling.
- Jesus Moreno, Víctor H. Champac, Michel Renovell:
A new methodology for realistic open defect detection probability evaluation under process variations.
- Julien Guilhemsang, Olivier Héron, Nicolas Ventroux, Olivier Goncalves, Alain Giulieri:
Impact of the application activity on intermittent faults in embedded systems.
- Sreenivas Gangadhar, Spyros Tragoudas:
An analytical method for estimating SET propagation.
- Celestino V. Martins, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors.
- Jeffrey F. Wheeldon:
Calibrated high-efficiency testing and modelling methodologies for concentrated multi-junction solar cells.
- Shobha Vasudevan:
Coverage closure in SoC verification: Are we chasing a mirage?
- Kyoung Youn Cho, Rajagopalan Srinivasan:
A scan cell architecture for inter-clock at-speed delay testing.
- Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu:
Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips.
- Dilip K. Bhavsar:
Harmony Widget for X-free scan testing.
- Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux:
Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure.
- Michail Maniatakos, Yiorgos Makris, Prabhakar Kudva, Bruce M. Fleischer:
Exponent monitoring for low-cost concurrent error detection in FPU control logic.
- Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal:
Enhancing online error detection through area-efficient multi-site implications.
- Priyadharshini Shanmugasundaram, Vishwani D. Agrawal:
Dynamic scan clock control for test time reduction maintaining peak power limit.
- Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick:
Structural tests of slave clock gating in low-power flip-flop.
- Nader Alawadhi, Ozgur Sinanoglu:
Revival of partial scan: Test cube analysis driven conversion of flip-flops.
- Dongsoo Lee, Sang Phill Park, Ashish Goel, Kaushik Roy:
Memory-based embedded digital ATE.
- Songwei Pei, Huawei Li, Xiaowei Li:
A unified test architecture for on-line and off-line delay fault detections.
- Ujjwal Guin, Chen-Huan Chiang:
Design for Bit Error Rate estimation of high speed serial links.
- Srinivasulu Alampally, R. T. Venkatesh, P. Shanmugasundaram, Rubin A. Parekhji, V. D. Agrawal:
An efficient test data reduction technique through dynamic pattern mixing across multiple fault models.
- Kameshwar Chandrasekar, Surendra Bommu, Sanjay Sengupta:
Low Coverage Analysis using dynamic un-testability debug in ATPG.
- Jia Li, Yu Huang, Dong Xiang:
Prediction of compression bound and optimization of compression architecture for linear decompression-based schemes.
- Yasuhiro Takahashi, Akinori Maeda:
Multi Domain Test: Novel test strategy to reduce the Cost of Test.
- Junxia Ma, Nisar Ahmed, Mohammad Tehranipoor:
Low-cost diagnostic pattern generation and evaluation procedures for noise-related failures.
- W.-A. Lin, C.-C. Lee, J.-L. Huang:
Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs.
- Hideo Okawara:
Practical signal processing at mixed signal test venues - Trend removal, noise reduction, wideband signal capturing -.
- LeRoy Winemberg, Mohammad Tehranipoor:
Special session: Hot topic: Smart silicon.
- Anne Gattiker:
Invited paper: Yin and Yang of embedded sensors for post-scaling-era.
- Cheng-Wen Wu:
Special session: Hot topic design and test of 3D and emerging memories.