VTS 2012: Maui, Hawaii, USA

30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012. IEEE 2012, ISBN 978-1-4673-1074-1

BIST

Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie:
Test generator with preselected toggling for low power built-in self-test. 1-6
Hyunjin Kim, Jacob A. Abraham:
A Built-In Self-Test scheme for DDR memory output timing test and measurement. 7-12
Mayur Bubna, Kaushik Roy, Ashish Goel:
HBIST: An approach towards zero external test cost. 13-18

Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Michel Renovell, Vincent Kerzerho, Olivier Potin, Christophe Kelma:
Smart selection of indirect parameters for DC-based alternate RF IC testing. 19-24
Nourredine Akkouche, Salvador Mir, Emmanuel Simeu, Mustapha Slamani:
Analog/RF test ordering in the early stages of production testing. 25-30
Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai:
A SAR ADC missing-decision level detection and removal technique. 31-36

Amit Ranjan Trivedi, Saibal Mukhopadhyay:
Self-adaptive power gating with test circuit for on-line characterization of energy inflection activity. 38-43
Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, Valeria Bertacco:
Comprehensive online defect diagnosis in on-chip networks. 44-49
D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich:
A pseudo-dynamic comparator for error detection in fault tolerant architectures. 50-55

Afsaneh Nassery, Srinath Byregowda, Sule Ozev, Marian Verhelst, Mustapha Slamani:
Built-in-Self Test of transmitter I/Q mismatch using self-mixing envelope detector. 56-61
Dzmitry Maliuk, Nathan Kupp, Yiorgos Makris:
Towards a fully stand-alone analog/RF BIST: A cost-effective implementation of a neural classifier. 62-67
Syed Askari, Mehrdad Nourani, Mini Rawat:
An on-chip NBTI monitor for estimating analog circuit degradation. 68-73

Eun Jung Jang, Anne Gattiker, Sani R. Nassif, Jacob A. Abraham:
An oscillation-based test structure for timing information extraction. 74-79
Sreejit Chakravarty, Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, Fan Yang, H. Guo, R. Lai, D. Li:
Silicon evaluation of faster than at-speed transition delay tests. 80-85
Michihiro Shintani, Takashi Sato:
A Bayesian-based process parameter estimation using IDDQ current signature. 86-91

Onnik Yaglioglu, Ben Eldridge:
Direct connection and testing of TSV and microbump devices using NanoPierce™ contactor for 3D-IC integration. 96-101
Yong-Xiao Chen, Yu-Jen Huang, Jin-Fu Li:
Test cost optimization technique for the pre-bond test of 3D ICs. 102-107
Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu:
Cost modeling and analysis for interposer-based three-dimensional IC. 108-113

Baris Arslan, Alex Orailoglu:
Delay test resource allocation and scheduling for multiple frequency domains. 114-119
Xi Qian, Chao Han, Adit D. Singh:
Detection of gate-oxide defects with timing tests at reduced power supply. 120-126
Francisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu:
Small-delay defects detection under process variation using Inter-Path Correlation. 127-132

Ji Hwan (Paul) Chun, Siew Mooi Lim, Shao Chee Ong, Jae Wook Lee, Jacob A. Abraham:
Test of phase interpolators in high speed I/Os using a sliding window search. 134-139
Nicholas Tzou, Thomas Moon, Xian Wang, Hyun Woo Choi, Abhijit Chatterjee:
Dual-frequency incoherent subsampling driven test response acquisition of spectrally sparse wideband signals with enhanced time resolution. 140-145
Thomas Moon, Nicholas Tzou, Xian Wang, Hyun Woo Choi, Abhijit Chatterjee:
Low-cost high-speed pseudo-random bit sequence characterization using nonuniform periodic sampling in the presence of noise. 146-151

Peter Wohl, John A. Waicukauski, J. E. Colburn:
Enhancing testability by structured partial scan. 152-157
Geewhun Seok, Hong Kim, Baker Mohammad:
Write-through method for embedded memory with compression Scan-based testing. 158-163
Masoud Zamani, Mehdi Baradaran Tahoori, Krishnendu Chakrabarty:
Ping-pong test: Compact test vector generation for reversible circuits. 164-169

Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker:
SAT-ATPG using preferences for improved detection of complex defect mechanisms. 170-175
Irith Pomeranz:
Static test compaction for transition faults under the hazard-based detection conditions. 176-181
Jinsuk Chung, Nur A. Touba:
Exploiting X-correlation in output compression via superset X-canceling. 182-187

Wei Zhao, Sreejit Chakravarty, Junxia Ma, Narendra Devta-Prasanna, Fan Yang, Mohammad Tehranipoor:
A novel method for fast identification of peak current during test. 191-196
Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara:
A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits. 197-202
Yang Zhao, Lisa Grenier, Amitava Majumdar:
Power Characterization of Embedded SRAMs for Power Binning. 203-208

Peilin Song, Franco Stellari:
Tester-based optical and electrical diagnostic system and techniques. 209-214
Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram:
A SMT-based diagnostic test generation method for combinational circuits. 215-220
Lixing Zhao, Vishwani D. Agrawal:
Net diagnosis using stuck-at and transition fault models. 221-226

Panagiota Papavramidou, Michael Nicolaidis:
Test algorithms for ECC-based memory repair in nanotechnologies. 228-233
Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu:
A Memory Failure Pattern Analyzer for memory diagnosis and repair. 234-239
Peyman Pouyan, Esteve Amat, Antonio Rubio:
Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime. 240-245

Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Are advanced DfT structures sufficient for preventing scan-attacks? 246-251
Yier Jin, Yiorgos Makris:
Proof carrying-based information flow tracking for data secrecy protection and hardware trust. 252-257
Patricia S. Lee, Ian G. Harris:
Test generation for subtractive specification errors. 258-263

Wen Yueh, Subho Chatterjee, Amit Ranjan Trivedi, Saibal Mukhopadhyay:
On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk. 264-269
Shreepad Panth, Sung Kyu Lim:
Transition delay fault testing of 3D ICs with IR-drop study. 270-275
Sushmita Kadiyala Rao, Chaitra Sathyanarayana, Ajay Kallianpur, Ryan Robucci, Chintan Patel:
Estimating Power Supply Noise and its impact on path delay. 276-281

V. Prasanth, Virendra Singh, Rubin A. Parekhji:
Derating based hardware optimizations in soft error tolerant designs. 282-287
Suraj Sindia, Vishwani D. Agrawal:
Towards spatial fault resilience in array processors. 288-293
Junyoung Park, Jacob A. Abraham:
An aging-aware flip-flop design based on accurate, run-time failure prediction. 294-299

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