Siddika Berna Örs

	2009
16		Atilla Elçi, Oleg B. Makarevich, Mehmet A. Orgun, Alexander Chefranov, Josef Pieprzyk, Yuri Anatolievich Bryukhomitsky, Siddika Berna Örs: Proceedings of the 2nd International Conference on Security of Information and Networks, SIN 2009, Gazimagusa, North Cyprus, October 6-10, 2009 ACM 2009
	2008
15		Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid Verbauwhede, Siddika Berna Örs: Low-cost implementations of NTRU for pervasive security. ASAP 2008: 79-84
14		Keklik Alptekin Bayam, Siddika Berna Örs: Differential Power Analysis resistant hardware implementation of the RSA cryptosystem. ISCAS 2008: 3314-3317
13		Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle: Hardware implementation of an elliptic curve processor over GF(p) with Montgomery modular multiplier. IJES 3(4): 229-240 (2008)
	2007
12		Elke De Mulder, Siddika Berna Örs, Bart Preneel, Ingrid Verbauwhede: Differential power and electromagnetic attacks on a FPGA implementation of elliptic curve cryptosystems. Computers & Electrical Engineering 33(5-6): 367-382 (2007)
	2004
11		Nele Mentens, Siddika Berna Örs, Bart Preneel: An FPGA implementation of an elliptic curve processor GF(2m). ACM Great Lakes Symposium on VLSI 2004: 454-457
10		François-Xavier Standaert, Siddika Berna Örs, Bart Preneel: Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? CHES 2004: 30-44
9		Lejla Batina, Geeke Bruin-Muurling, Siddika Berna Örs: Flexible Hardware Design for RSA and Elliptic Curve Cryptosystems. CT-RSA 2004: 250-263
8		François-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart Preneel: Power Analysis Attacks Against FPGA Implementations of the DES. FPL 2004: 84-94
7		Siddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel: Power-Analysis Attack on an ASIC AES implementation. ITCC (2) 2004: 546-552
6		Nele Mentens, Siddika Berna Örs, Bart Preneel, Joos Vandewalle: An FPGA Implementation of a Montgomery Multiplier Over GF(2^m). Computers and Artificial Intelligence 23(5): (2004)
	2003
5		Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle: Hardware Implementation of an Elliptic Curve Processor over GF(p). ASAP 2003: 433-443
4		Siddika Berna Örs, Elisabeth Oswald, Bart Preneel: Power-Analysis Attacks on an FPGA - First Experimental Results. CHES 2003: 35-50
3		Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle: Hardware Implementation of a Montgomery Modular Multiplier in a Systolic Array. IPDPS 2003: 184
2		Lejla Batina, Siddika Berna Örs, Bart Preneel, Joos Vandewalle: Hardware architectures for public key cryptography. Integration 34(1-2): 1-64 (2003)
	1999
1		Siddika Berna Örs, Ahmet Dervisoglu: Modeling Bit Multiplication Blocks for DSP Applications Using VHDL. EUROMICRO 1999: 1402-1405

Coauthor Index

1	Ali Can Atici	[15]
2	Lejla Batina	[2] [3] [5] [9] [13] [15]
3	Keklik Alptekin Bayam	[14]
4	Geeke Bruin-Muurling	[9]
5	Yuri Anatolievich Bryukhomitsky	[16]
6	Alexander Chefranov	[16]
7	Ahmet Dervisoglu	[1]
8	Atilla Elçi	[16]
9	Junfeng Fan	[15]
10	Frank K. Gürkaynak	[7]
11	Oleg B. Makarevich	[16]
12	Nele Mentens	[6] [11]
13	Elke De Mulder	[12]
14	Mehmet A. Orgun	[16]
15	Elisabeth Oswald	[4] [7]
16	Josef Pieprzyk	[16]
17	Bart Preneel	[2] [3] [4] [5] [6] [7] [8] [10] [11] [12] [13]
18	Jean-Jacques Quisquater	[8]
19	François-Xavier Standaert	[8] [10]
20	Joos Vandewalle	[2] [3] [5] [6] [13]
21	Ingrid Verbauwhede	[12] [15]

Colors in the list of coauthors