 | 2009 |
| 22 |  | Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
Design and implementation of a queue compiler.
Microprocessors and Microsystems - Embedded Hardware Design 33(2): 129-138 (2009) |
| 21 |  | Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
Efficient compilation for queue size constrained queue processors.
Parallel Computing 35(4): 213-225 (2009) |
| 20 |  | Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
Compiler Support for Code Size Reduction Using a Queue-Based Processor.
T. HiPEAC 2: 269-285 (2009) |
| 2008 |
| 19 |  | Hiroki Hoshino,
Ben A. Abderazek,
Kenichi Kuroda:
Advanced Optimization and Design Issues of a 32-Bit Embedded Processor Based on Produced Order Queue Computation Model.
EUC (1) 2008: 16-22 |
| 18 |  | Taichi Maekawa,
Ben A. Abderazek,
Kenichi Kuroda:
Single Instruction Dual-Execution Model Processor Architecture.
EUC (1) 2008: 30-36 |
| 17 |  | Arquimedes Canedo,
Masahiro Sowa,
Ben A. Abderazek:
Quantitative Evaluation of Common Subexpression Elimination on Queue Machines.
ISPAN 2008: 25-30 |
| 16 |  | Ben A. Abderazek,
Arquimedes Canedo,
Tsutomu Yoshinaga,
Masahiro Sowa:
The QC-2 parallel Queue processor architecture.
J. Parallel Distrib. Comput. 68(2): 235-245 (2008) |
| 15 |  | Md. Musfiquzzaman Akanda,
Ben A. Abderazek,
Masahiro Sowa:
Dual-execution mode processor architecture.
The Journal of Supercomputing 44(2): 103-125 (2008) |
| 2007 |
| 14 |  | Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model.
EUC 2007: 196-208 |
| 13 |  | Ben A. Abderazek,
Mushfiquzzaman Akanda,
Tsutomu Yoshinaga,
Masahiro Sowa:
Mathematical Model for Multiobjective Synthesis of NoC Architectures.
ICPP Workshops 2007: 36 |
| 12 |  | Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
New Code Generation Algorithm for QueueCoreAn Embedded Processor with High ILP.
PDCAT 2007: 185-192 |
| 11 |  | Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
Queue Register File Optimization Algorithm for QueueCore Processor.
SBAC-PAD 2007: 169-176 |
| 10 |  | Yuki Nakanishi,
Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
Optimizing Reaching Definitions Overhead in Queue Processors.
JCIT 2(4): 36-40 (2007) |
| 2006 |
| 9 |  | Ben A. Abderazek,
Tsutomu Yoshinaga,
Masahiro Sowa:
Scalable Core-Based Methodology and Synthesizable Core for Systematic Design.
ICPP Workshops 2006: 345-352 |
| 8 |  | Md. Musfiquzzaman Akanda,
Ben A. Abderazek,
Masahiro Sowa:
On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation.
ISPA Workshops 2006: 37-46 |
| 7 |  | Ben A. Abderazek,
Sotaro Kawata,
Masahiro Sowa:
Design and architecture for an embedded 32-bit QueueCore.
J. Embedded Computing 2(2): 191-205 (2006) |
| 6 |  | Ben A. Abderazek,
Tsutomu Yoshinaga,
Masahiro Sowa:
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
The Journal of Supercomputing 38(1): 3-15 (2006) |
| 2005 |
| 5 |  | Ben A. Abderazek,
Sotaro Kawata,
Tsutomu Yoshinaga,
Masahiro Sowa:
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.
EUC 2005: 340-349 |
| 4 |  | Md. Musfiquzzaman Akanda,
Ben A. Abderazek,
Sotaro Kawata,
Masahiro Sowa:
An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture.
EUC 2005: 77-86 |
| 3 |  | Masahiro Sowa,
Ben A. Abderazek,
Tsutomu Yoshinaga:
Parallel Queue Processor Architecture Based on Produced Order Computation Model.
The Journal of Supercomputing 32(3): 217-229 (2005) |
| 2003 |
| 2 |  | Ben A. Abderazek,
Soichi Shigeta,
Tsutomu Yoshinaga,
Masahiro Sowa:
On the Design of a Register Queue Based Processor Architecture (FaRM-rq).
ISPA 2003: 248-262 |
| 2002 |
| 1 |  | Masahiro Sowa,
Ben A. Abderazek,
Soichi Shigeta,
Kirilka Nikolova,
Tsutomu Yoshinaga:
Proposal and Design of a Parallel Queue Processor Architecture (PQP).
IASTED PDCS 2002: 549-554 |