Nainesh Agarwal

	2009
9		Nainesh Agarwal, Nikitas J. Dimopoulos: Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing. SAMOS 2009: 108-117
	2008
8		Nainesh Agarwal, Nikitas J. Dimopoulos: FSMD partitioning for low power using simulated annealing. ISCAS 2008: 1244-1247
7		Nainesh Agarwal, Nikitas J. Dimopoulos: FSMD Partitioning for Low Power Using ILP. ISVLSI 2008: 63-68
	2007
6		Nainesh Agarwal, Nikitas J. Dimopoulos: Towards Automated Power Gating of Registers using CoDeL. ISCAS 2007: 1629-1632
5		Nainesh Agarwal, Nikitas J. Dimopoulos: DSPstone Benchmark of CoDeL's Automated Clock Gating Platform. ISVLSI 2007: 508-509
4		Nainesh Agarwal, Nikitas J. Dimopoulos: Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction. SAMOS 2007: 294-303
	2006
3		Nainesh Agarwal, Nikitas J. Dimopoulos: Power efficient rapid hardware development using CoDel and automated clock gating. ISCAS 2006
2		Nainesh Agarwal, Nikitas J. Dimopoulos: Efficient Automated Clock Gating Using CoDeL. SAMOS 2006: 79-88
	2004
1		Nainesh Agarwal, Nikitas J. Dimopoulos: Using CoDeL to Rapidly Prototype Network Processsor Extensions. SAMOS 2004: 333-342

Coauthor Index

1

Nikitas J. Dimopoulos

[1] [2] [3] [4] [5] [6] [7] [8] [9]