M. Agarwala

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1995

1 M. Agarwala, Poras T. Balsara: An architecture for a DSP field-programmable gate array. IEEE Trans. VLSI Syst. 3(1): 136-141 (1995)

	1995
1		M. Agarwala, Poras T. Balsara: An architecture for a DSP field-programmable gate array. IEEE Trans. VLSI Syst. 3(1): 136-141 (1995)

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