V. D. Agrawal

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2003

2 V. D. Agrawal: Editorial. J. Electronic Testing 19(5): 495 (2003)

1998

1 S. Bose, P. Agrawal, V. D. Agrawal: A rated-clock test method for path delay faults. IEEE Trans. VLSI Syst. 6(2): 323-331 (1998)

	2003
2		V. D. Agrawal: Editorial. J. Electronic Testing 19(5): 495 (2003)
	1998
1		S. Bose, P. Agrawal, V. D. Agrawal: A rated-clock test method for path delay faults. IEEE Trans. VLSI Syst. 6(2): 323-331 (1998)

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