Nisar Ahmed

	2008
18		Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed: Low-Transition Test Pattern Generation for BIST-Based Applications. IEEE Trans. Computers 57(3): 303-315 (2008)
	2007
17		Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram: Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design. DAC 2007: 533-538
16		Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram: Supply Voltage Noise Aware ATPG for Transition Delay Faults. VTS 2007: 179-186
15		Mian M. Awais, Shafay Shamail, Nisar Ahmed: Dimensionally reduced Krylov subspace model reduction for large scale systems. Applied Mathematics and Computation 191(1): 21-30 (2007)
14		Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler: Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 896-906 (2007)
	2006
13		Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram: Timing-based delay test for screening small delay defects. DAC 2006: 320-325
12		Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram: A novel framework for faster-than-at-speed delay test considering IR-drop effects. ICCAD 2006: 198-203
11		Nisar Ahmed, Mohammad Tehranipoor: Improving Transition Delay Test Using a Hybrid Method. IEEE Design & Test of Computers 23(5): 402-412 (2006)
	2005
10		Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed: Low Transition LFSR for BIST-Based Applications. Asian Test Symposium 2005: 138-143
9		Nisar Ahmed, Mohammad Tehranipoor: Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. DFT 2005: 187-198
8		Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic: At-Speed Transition Fault Testing With Low Speed Scan Enable. VTS 2005: 42-47
7		Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed: Pattern Generation and Estimation for Power Supply Noise Analysis. VTS 2005: 439-444
	2004
6		Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani: Low power pattern generation for BIST architecture. ISCAS (2) 2004: 689-692
5		Nisar Ahmed, Mohammad H. Tehranipour, Dian Zhou, Mehrdad Nourani: Frequency driven repeater insertion for deep submicron. ISCAS (5) 2004: 181-184
4		Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani: Testing SoC interconnects for signal integrity using extended JTAG architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 800-811 (2004)
	2003
3		Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani: Extending JTAG for Testing Signal Integrity in SoCs. DATE 2003: 10218-10223
2		Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani: Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity. ICCD 2003: 554-
1		Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani: Testing SoC Interconnects for Signal Integrity Using Boundary Scan. VTS 2003: 158-172

Coauthor Index

1	Mian M. Awais	[15]
2	Kenneth M. Butler	[14]
3	Vinay Jayaram	[12] [13] [16] [17]
4	Mehrdad Nourani	[1] [2] [3] [4] [5] [6] [7] [10] [18]
5	James F. Plusquellic (Jim Plusquellic)	[8]
6	C. P. Ravikumar	[8] [14]
7	Shafay Shamail	[15]
8	Mohammad Tehranipoor	[7] [8] [9] [10] [11] [12] [13] [14] [16] [17] [18]
9	Mohammad H. Tehranipour	[1] [2] [3] [4] [5] [6]
10	Dian Zhou	[5]

Colors in the list of coauthors