Rob Aitken
List of publications from the DBLP Bibliography Server - FAQ
| 2009 | ||
|---|---|---|
| 64 | Shidhartha Das, David Blaauw, David Bull, Krisztián Flautner, Rob Aitken: Addressing design margins through error-tolerant circuits. DAC 2009: 11-12 | |
| 63 | Vikas Chandra, Robert C. Aitken: Impact of voltage scaling on nanoscale SRAM reliability. DATE 2009: 387-392 | |
| 62 | Robert C. Aitken: The challenges of correlating silicon and models in high variability CMOS processes. ISPD 2009: 181-182 | |
| 61 | Robert C. Aitken: DFX and Productivity. VLSI Design 2009: 8 | |
| 2008 | ||
| 60 | Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh: DFM in practice: hit or hype? DAC 2008: 898-899 | |
| 59 | S. Turnoy, Peter Wintermayr, Robert C. Aitken, Rudy Lauwereins, J. Tracy Weed, V. Kiefer, J. Hartmann: Panel Session - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm. DATE 2008: 510 | |
| 58 | Vikas Chandra, Robert C. Aitken: Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS. DFT 2008: 114-122 | |
| 57 | Rob Aitken, Jerry Bautista, Wojciech Maly, Jan M. Rabaey: More Moore: foolish, feasible, or fundamentally different? ICCAD 2008: 9 | |
| 56 | Rob Aitken, Erik Jan Marinissen: Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis. IEEE Design & Test of Computers 25(3): 206-207 (2008) | |
| 2007 | ||
| 55 | Robert C. Aitken, Sachin Idgunji: Worst-case design and margin for embedded SRAM. DATE 2007: 1289-1294 | |
| 54 | Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki: DFM/DFY: should you trust the surgeon or the family doctor? DATE 2007: 439-442 | |
| 53 | Robert C. Aitken: Defect or Variation? Characterizing Standard Cell Behavior at 90nm and below. ISQED 2007: 693-698 | |
| 52 | Dimitris Gizopoulos, Robert C. Aitken, S. Kundu: Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems". IEEE Trans. VLSI Syst. 15(5): 493-494 (2007) | |
| 2006 | ||
| 51 | Enrico Macii, Massoud Pedram, Dirk Friebel, Robert C. Aitken, Antun Domic, Roberto Zafalon: Low-power design tools: are EDA vendors taking this matter seriously? DATE 2006: 1227 | |
| 50 | Robert C. Aitken: Reliability Issues for Embedded SRAM at 90nm and Below. IOLTS 2006: 75 | |
| 49 | Robert C. Aitken: DFM Metrics for Standard Cells. ISQED 2006: 491-496 | |
| 2005 | ||
| 48 | Robert C. Aitken, Betina Hold: Modeling Soft-Error Susceptibility for IP Blocks. IOLTS 2005: 70-73 | |
| 47 | Robert C. Aitken: ITC is Cool. IEEE Design & Test of Computers 22(6): 616 (2005) | |
| 2004 | ||
| 46 | Robert C. Aitken, Fidel Muradali: From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions. DATE 2004: 2 | |
| 45 | Robert C. Aitken: A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories. ITC 2004: 997-1005 | |
| 44 | Robert C. Aitken: Redundancy & It's Not Just for Defects Anymore. MTDT 2004: 117-120 | |
| 43 | Rob Aitken, Stefan Eichenberger, Gary Maier, Sandip Kundu, Hank Walker: ITC 2003 Roundtable: Design for Manufacturability. IEEE Design & Test of Computers 21(2): 144-156 (2004) | |
| 42 | Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken: ITC 2003 panels: Part 1. IEEE Design & Test of Computers 21(2): 160-163 (2004) | |
| 41 | Rob Aitken: Test at Gbps: Megaproblem or micromanagement? IEEE Design & Test of Computers 21(4): 344- (2004) | |
| 2003 | ||
| 40 | Rob Aitken, Neeraj Dogra, Dhrumil Gandhi, Scott Becker: Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator. DFT 2003: 467-474 | |
| 39 | Robert C. Aitken: DFM: The Real 90nm Hurdle. ITC 2003: 1313 | |
| 38 | Robert C. Aitken: Silicon IP And Successful DFM. ITC 2003: 1314 | |
| 37 | Robert C. Aitken: Applying Defect-Based Test to Embedded Memories in a COT Model. MTDT 2003: 72- | |
| 36 | Robert C. Aitken, Gordon W. Roberts: ITC 2003: Breaking Test Interface Bottlenecks. IEEE Design & Test of Computers 20(5): 54- (2003) | |
| 35 | Gordon W. Roberts, Robert C. Aitken: ITC Highlights. IEEE Design & Test of Computers 20(5): 55-57 (2003) | |
| 2002 | ||
| 34 | Robert C. Aitken: Test Generation and Fault Modeling for Stress Testing (invited). ISQED 2002: 95-99 | |
| 33 | Robert C. Aitken, Mustapha Slamani, H. Ding, William R. Eisenstadt, Sanghoon Choi, John McLaughlin: Wireless Test. VTS 2002: 173-174 | |
| 32 | Julie Segal, Rene Segers, Rob Aitken, S. Eichenberge, A. Gattike, M. Millegen, R. Seger, S. Venkataraman: Test as a Key Enabler for Faster Yield Ramp-Up. VTS 2002: 177-180 | |
| 31 | Robert C. Aitken, Donald L. Wheater: Guest Editors' Introduction: Stressing the Fundamentals. IEEE Design & Test of Computers 19(5): 54-55 (2002) | |
| 2000 | ||
| 30 | Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman: Current ratios: a self-scaling technique for production IDDQ testing. ITC 2000: 1148-1156 | |
| 1999 | ||
| 29 | Robert C. Aitken: It Makes Sense to Combine DFT and DFR/DFY. ITC 1999: 1143 | |
| 28 | Robert C. Aitken, Fidel Muradali: Trends in SLI design and their effect on test. ITC 1999: 628-637 | |
| 27 | Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman: Current ratios: a self-scaling technique for production I_DDQ testing. ITC 1999: 738-746 | |
| 26 | Robert C. Aitken: Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage. VTS 1999: 128-134 | |
| 25 | Robert C. Aitken: Nanometer Technology Effects on Fault Models for IC Testing. IEEE Computer 32(11): 46-51 (1999) | |
| 1998 | ||
| 24 | Robert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne Wolf: How will CAD handle billion-transistor systems? (panel). ICCAD 1998: 5 | |
| 23 | Robert C. Aitken: On-chip versus off-chip test: an artificial dichotomy. ITC 1998: 1146 | |
| 1997 | ||
| 22 | Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly: So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. ITC 1997: 1037-1038 | |
| 21 | Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian: Power Dissipation During Testing: Should We Worry About it? VTS 1997: 456-457 | |
| 20 | Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken: An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing. VTS 1997: 459 | |
| 19 | Robert C. Aitken: Modeling the Unmodelable: Algorithmic Fault Diagnosis. IEEE Design & Test of Computers 14(3): 98-103 (1997) | |
| 1996 | ||
| 18 | Peter C. Maxwell, Robert C. Aitken, Kathleen R. Kollitz, Allen C. Brown: IDDQ and AC Scan: The War Against Unmodelled Defects. ITC 1996: 250-258 | |
| 17 | Robert C. Aitken: Modelling the Unmodellable: Algorithmic Fault Diagnosis. ITC 1996: 931 | |
| 16 | Robert C. Aitken, J. Hutcheson, N. Murthy, Phil Nigh, Nicholas Sporck: Volume Manufacturing - ICs and Boards: DFT to the Rescue? VTS 1996: 212-213 | |
| 15 | Robert C. Aitken: When tools cry wolf: Testability pitfalls of synthesized designs. IEEE Design & Test of Computers 13(4): 96- (1996) | |
| 1995 | ||
| 14 | Robert C. Aitken: Finding Defects with Fault Models. ITC 1995: 498-505 | |
| 13 | Robert C. Aitken: An Overview of Test Synthesis Tools. IEEE Design & Test of Computers 12(2): 8-15 (1995) | |
| 1994 | ||
| 12 | Peter C. Maxwell, Robert C. Aitken, Leendert M. Huisman: The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability. ITC 1994: 739-746 | |
| 1993 | ||
| 11 | Robert C. Aitken: BP-1992 A Comparison of Defect Models for Fault Location with IDDQ Measurements. ITC 1993: 1051-1060 | |
| 10 | Peter C. Maxwell, Robert C. Aitken: Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic. ITC 1993: 63-72 | |
| 9 | Peter C. Maxwell, Robert C. Aitken: Test Sets and Reject Rates: All Fault Coverages are Not Created Equal. IEEE Design & Test of Computers 10(1): 42-51 (1993) | |
| 1992 | ||
| 8 | Peter C. Maxwell, Robert C. Aitken, Vic Johansen, Inshen Chiang: The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need? ITC 1992: 168-177 | |
| 7 | Robert C. Aitken: A Comparison of Defect Models for Fault Location with IDDQ Measurements. ITC 1992: 778-787 | |
| 6 | Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal: Using an asymmetric error model to study aliasing in signature analysis registers. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 16-25 (1992) | |
| 5 | Peter C. Maxwell, Robert C. Aitken: IDDQ testing as a component of a test suite: The need for several fault coverage metrics. J. Electronic Testing 3(4): 305-316 (1992) | |
| 4 | Robert C. Aitken: Diagnosis of leakage faults with IDDQ. J. Electronic Testing 3(4): 367-375 (1992) | |
| 1991 | ||
| 3 | Peter C. Maxwell, Robert C. Aitken, Vic Johansen, Inshen Chiang: The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%? ITC 1991: 358-364 | |
| 2 | Robert C. Aitken: Fault Location with Current Monitoring. ITC 1991: 623-632 | |
| 1989 | ||
| 1 | Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal: : Experiments on Aliasing in Signature Analysis Registers. ITC 1989: 344-354 | |