Asim J. Al-Khalili

A. J. Al-Khalili

	2009
33		Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria: An interconnect-aware delay model for dynamic voltage scaling in NM technologies. ACM Great Lakes Symposium on VLSI 2009: 45-50
	2006
32		A. J. Al-Khalili: A CAD Tool for Scalable, Variable Architecture Floating-Point Adder Generator. AICCSA 2006: 74-79
31		Asim J. Al-Khalili: A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers. ICN/ICONS/MCL 2006: 183
30		Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria: Zero skew differential clock distribution network. ISCAS 2006
	2005
29		Shaoqiang Bi, Warren J. Gross, Wei Wang, Asim J. Al-Khalili, M. N. S. Swamy: An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. IWSOC 2005: 396-399
28		Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili: Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1637-1643 (2005)
27		Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili: Delay analysis of CMOS gates using modified logical effort model. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 937-947 (2005)
	2004
26		Shaoqiang Bi, Wei Wang, Asim J. Al-Khalili: Modulo deflation in (2n+1, 2n, 2n-1) converters. ISCAS (2) 2004: 429-432
	2003
25		Asim J. Al-Khalili, Aiping Hu: Design of a 32-bit squarer - exploiting addition redundancy. ISCAS (5) 2003: 325-328
24		Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili: Technology-portable analytical model for DSM CMOS inverter transition-time estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1177-1187 (2003)
23		Cheng-Yu Pai, Asim J. Al-Khalili, William E. Lynch: Low-Power Constant-Coefficient Multiplier Generator. VLSI Signal Processing 35(2): 187-194 (2003)
	2002
22		Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili: Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 119-125
	2001
21		R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah: A Low Power Approach to Floating Point Adder Design for DSP Applications. VLSI Signal Processing 27(3): 195-213 (2001)
	1999
20		R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: Power implications of precision limited arithmetic in floating point FIR filters. ISCAS (1) 1999: 165-168
19		Adnan Kabbani, A. J. Al-Khalili: Dynamic CMOS noise immunity estimation in submicron regime. ISCAS (1) 1999: 529-532
18		Adnan Kabbani, A. J. Al-Khalili: Estimation of ground bounce effects on CMOS circuits. ISCAS (1) 1999: 533-536
17		R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: An IEEE Compliant Floating Point MAF. VLSI 1999: 149-160
16		Jacob Augustine, William E. Lynch, Yuke Wang, Asim J. Al-Khalili: Lossy Compression of Images Using Logic Minimization. VLSI Design 1999: 538-543
	1998
15		R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili: A Low Power Floating Point Accumulator. VLSI Design 1998: 330-
	1997
14		R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: A Low Power Approach to Floating Point Adder Design. ICCD 1997: 178-185
13		R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. ISLPED 1997: 235-238
	1996
12		R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili: Energy delay analysis of partial product reduction methods for parallel multiplier implementation. ISLPED 1996: 201-204
	1995
11		Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri: Area efficient computing structures for concurrent error detection in systolic arrays. VLSI Signal Processing 10(3): 237-260 (1995)
10		Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili: Design techniques for fault-tolerant systolic arrays. VLSI Signal Processing 11(1-2): 151-168 (1995)
	1992
9		F. Rouatbi, Baher Haroun, Asim J. Al-Khalili: Power estimation tool for sub-micron CMOS VLSI circuits. ICCAD 1992: 204-209
8		Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri: Design Methodology for Fault-Tolerant Systolic Array Architectures. ICPP (2) 1992: 267-274
	1991
7		Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri: Area Efficient Computing Structures for Concurrent Error Detection in Systolic Architectures. ICPP (1) 1991: 484-491
6		Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri: On the Design of Optimal Fault-Tolerant Systolic Array Architecures. IPPS 1991: 352-357
	1990
5		Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri: Design of optimal systolic arrays: a systematic approach. SPDP 1990: 166-173
4		Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili: A module generator for optimized CMOS buffers. IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 1028-1046 (1990)
	1989
3		Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili: A Module Generator for Optimized CMOS Buffers. DAC 1989: 245-250
	1984
2		Asim J. Al-Khalili: An Algorithm for an Intelligent Arabic Computer Terminal. International Journal of Man-Machine Studies 20(4): 331-341 (1984)
	1973
1		C. J. Macleod, Asim J. Al-Khalili: An On-Line Optimization Procedure for an Urban Traffic System. Optimization Techniques 1973: 31-41

Coauthor Index

1	Dhamin Al-Khalili	[3] [4] [10] [12] [13] [14] [15] [17] [20] [21] [22] [24] [27] [28]
2	Jacob Augustine	[16]
3	Shaoqiang Bi	[26] [29]
4	Michael Ogbonna Esonu	[5] [6] [7] [8] [10] [11]
5	Warren J. Gross	[29]
6	Salim Hariri	[5] [6] [7] [8] [10] [11]
7	Baher Haroun	[9]
8	Aiping Hu	[25]
9	Adnan Kabbani	[18] [19] [24] [27]
10	William E. Lynch	[16] [23]
11	C. J. Macleod	[1]
12	Mohamed Nekili	[22] [28]
13	Cheng-Yu Pai	[23]
14	R. V. K. Pillai	[12] [13] [14] [15] [17] [20] [21]
15	F. Rouatbi	[9]
16	Haydar Saaied	[22] [28] [30]
17	Yvon Savaria	[30] [33]
18	S. Y. A. Shah	[21]
19	M. N. S. Swamy	[29]
20	Yuke Wang	[16]
21	Wei Wang	[26] [29]
22	Houman Zarrabi	[30] [33]
23	Yong Zhu	[3] [4]

Colors in the list of coauthors