Moayad Fahim Ali

	2005
5		Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876
4		Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47
3		Alexander Smith, Andreas G. Veneris, Moayad Fahim Ali, Anastasios Viglas: Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1606-1621 (2005)
	2004
2		Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir: Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209
1		Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith: Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49

Coauthor Index

1	Magdy S. Abadir	[1] [2] [4] [5]
2	Rolf Drechsler	[1] [2] [4] [5]
3	Sean Safarpour	[1] [2] [4] [5]
4	Freescale Semiconductor	[1]
5	Alexander Smith	[1] [2] [3]
6	Andreas G. Veneris	[1] [2] [3] [4] [5]
7	Anastasios Viglas	[3]