 | 2009 |
|---|
| 8 |       | Mythri Alle,
Keshavan Varadarajan,
Alexander Fell,
S. K. Nandy,
Ranjani Narayan:
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures.
ARC 2009: 204-215 |
| 7 | | Adarsha Rao,
Mythri Alle,
Sainath V,
Reyaz Shaik,
Rajashekhar Chowhan,
S. Sankaraiah,
Sravanthi Mantha,
S. K. Nandy,
Ranjani Narayan:
An Input Triggered Polymorphic ASIC for H.264 Decoding.
ASAP 2009: 106-113 |
| 6 | | Alexander Fell,
Mythri Alle,
Keshavan Varadarajan,
Prasenjit Biswas,
Saptarsi Das,
Jugantor Chetia,
S. K. Nandy,
Ranjani Narayan:
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.
CASES 2009: 127-136 |
| 2008 |
|---|
| 5 | | Mythri Alle,
Keshavan Varadarajan,
Ramesh C. Ramesh,
Joseph Nimmy,
Alexander Fell,
Adarsha Rao,
S. K. Nandy,
Ranjani Narayan:
Synthesis of application accelerators on Runtime Reconfigurable Hardware.
ASAP 2008: 13-18 |
| 4 | | Joseph Nimmy,
C. Ramesh Reddy,
Keshavan Varadarajan,
Mythri Alle,
Alexander Fell,
S. K. Nandy,
Ranjani Narayan:
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.
ASAP 2008: 251-256 |
| 3 | | Adarsha Rao,
Mythri Alle,
S. K. Nandy,
Ranjani Narayan:
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders.
ASAP 2008: 287-292 |
| 2007 |
|---|
| 2 | | A. N. Satrawala,
Keshavan Varadarajan,
Mythri Alle,
S. K. Nandy,
Ranjani Narayan:
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.
FPL 2007: 558-561 |
| 2006 |
|---|
| 1 | | Mythri Alle,
Jayanta Biswas,
S. K. Nandy:
High Performance VLSI Architecture Design for H.264 CAVLC Decoder.
ASAP 2006: 317-322 |
