 | 2009 |
|---|
| 160 |       | Tomoya Ishimori,
Hideki Yamada,
Yuichiro Shibata,
Yasunori Osana,
Masato Yoshimi,
Yuri Nishikawa,
Hideharu Amano,
Akira Funahashi,
Noriko Hiroi,
Kiyoshi Oguri:
Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator.
ARC 2009: 368-373 |
| 159 | | Lei Zhao,
Hui Xu,
Naomi Seki,
Saito Yoshiki,
Yohei Hasegawa,
Kimiyoshi Usami,
Hideharu Amano:
Cache Controller Design on Ultra Low Leakage Embedded Processors.
ARCS 2009: 171-182 |
| 158 |  | Toru Sano,
Yoshiki Saito,
Hideharu Amano:
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors.
ERSA 2009: 112-118 |
| 157 | | Hideharu Amano:
Japanese Dynamically Reconfigurable Processors.
ERSA 2009: 19-28 |
| 156 | | Yoshiki Saito,
Toru Sano,
Masaru Kato,
Vasutan Tunbunheng,
Yoshihiro Yasuda,
Hideharu Amano:
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array.
ERSA 2009: 283-286 |
| 155 | | Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano,
Tsutomu Yoshinaga:
Prediction router: Yet another low latency on-chip router architecture.
HPCA 2009: 367-378 |
| 154 | | Michihiro Koibuchi,
Tomohiro Otsuka,
Hiroki Matsutani,
Hideharu Amano:
An on/off link activation method for low-power ethernet in PC clusters.
IPDPS 2009: 1-11 |
| 153 | | Vu Manh Tuan,
Naohiro Katsura,
Hiroki Matsutani,
Hideharu Amano:
Evaluation of a multicore reconfigurable architecture with variable core sizes.
IPDPS 2009: 1-8 |
| 152 | | Jose Miguel Montanana Aliaga,
Michihiro Koibuchi,
Takafumi Watanabe,
Tomoyuki Hiroyasu,
Hiroki Matsutani,
Hideharu Amano:
An On/Off Link Activation Method for Power Regulation in InfiniBand.
PDPTA 2009: 289-295 |
| 151 | | Kimiyoshi Usami,
Toshiaki Shirai,
Tasunori Hashida,
Hiroki Masuda,
Seidai Takeda,
Mitsutaka Nakata,
Naomi Seki,
Hideharu Amano,
Mitaro Namiki,
Masashi Imai,
Masaaki Kondo,
Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
VLSI Design 2009: 381-386 |
| 150 | | Hiroki Matsutani,
Michihiro Koibuchi,
Yutaka Yamada,
D. Frank Hsu,
Hideharu Amano:
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.
IEEE Trans. Parallel Distrib. Syst. 20(8): 1126-1141 (2009) |
| 149 | | Daihan Wang,
Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano:
A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs.
IEICE Transactions 92-D(4): 575-583 (2009) |
| 148 | | Hideharu Amano,
Tadao Nakamura:
Guest Editors' Introduction: ICFPT 2007.
TRETS 2(2): (2009) |
| 2008 |
|---|
| 147 | | Vu Manh Tuan,
Hideharu Amano:
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor.
ARC 2008: 171-182 |
| 146 | | Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano,
Daihan Wang:
Run-time power gating of on-chip routers using look-ahead routing.
ASP-DAC 2008: 55-60 |
| 145 | | Vu Manh Tuan,
Hideharu Amano:
A Method for Capturing State Data on Dynamically Reconfigurable Processors.
ERSA 2008: 208-214 |
| 144 | | Masaru Kato,
Yohei Hasegawa,
Hideharu Amano:
Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs.
ERSA 2008: 215-221 |
| 143 | | Toru Sano,
Masaru Kato,
Satoshi Tsutsumi,
Yohei Hasegawa,
Hideharu Amano:
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors.
FPL 2008: 215-220 |
| 142 | | Daihan Wang,
Hiroki Matsutani,
Hideharu Amano,
Michihiro Koibuchi:
A link removal methodology for Networks-on-Chip on reconfigurable systems.
FPL 2008: 269-274 |
| 141 | | Takashi Nishimura,
Keiichiro Hirai,
Yoshiki Saito,
Takuro Nakamura,
Yohei Hasegawa,
Satoshi Tsutsusmi,
Vasutan Tunbunheng,
Hideharu Amano:
Power reduction techniques for Dynamically Reconfigurable Processor Arrays.
FPL 2008: 305-310 |
| 140 | | Masato Yoshimi,
Yuri Nishikawa,
Yasunori Osana,
Akira Funahashi,
Yuichiro Shibata,
Hideki Yamada,
Noriko Hiroi,
Hiroaki Kitano,
Hideharu Amano:
Practical implementation of a network-based stochastic biochemical simulation system on an FPGA.
FPL 2008: 663-666 |
| 139 | | Naomi Seki,
Lei Zhao,
Jo Kei,
Daisuke Ikebuchi,
Yu Kojima,
Yohei Hasegawa,
Hideharu Amano,
Toshihiro Kashima,
Seidai Takeda,
Toshiaki Shirai,
Mitsutaka Nakata,
Kimiyoshi Usami,
Tetsuya Sunata,
Jun Kanai,
Mitaro Namiki,
Masaaki Kondo,
Hiroshi Nakamura:
A fine-grain dynamic sleep control scheme in MIPS R3000.
ICCD 2008: 612-617 |
| 138 | | Hiroki Matsutani,
Michihiro Koibuchi,
D. Frank Hsu,
Hideharu Amano:
Three-Dimensional Layout of On-Chip Tree-Based Networks.
ISPAN 2008: 281-288 |
| 137 | | Michihiro Koibuchi,
Hiroki Matsutani,
Hideharu Amano,
Timothy Mark Pinkston:
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip.
NOCS 2008: 13-22 |
| 136 | | Hiroki Matsutani,
Michihiro Koibuchi,
Daihan Wang,
Hideharu Amano:
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.
NOCS 2008: 23-32 |
| 135 | | Vasutan Tunbunheng,
Hideharu Amano:
A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays.
IEICE Transactions 91-D(11): 2655-2665 (2008) |
| 134 | | Vu Manh Tuan,
Hideharu Amano:
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors.
IEICE Transactions 91-D(12): 2793-2803 (2008) |
| 133 | | Vu Manh Tuan,
Hideharu Amano:
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors.
IEICE Transactions 91-D(9): 2312-2322 (2008) |
| 2007 |
|---|
| 132 | | Takamasa Kanamori,
Hideharu Amano,
Masatoshi Arai,
Daisuke Konno,
Tomomichi Nanba,
Yoshiaki Ajioka:
Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA.
CIT 2007: 567-572 |
| 131 | | Vu Manh Tuan,
Yohei Hasegawa,
Hideharu Amano:
Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor.
ERSA 2007: 203-206 |
| 130 | | Masato Yoshimi,
Yow Iwaoka,
Yuri Nishikawa,
Toshinori Kojima,
Yasunori Osana,
Akira Funahashi,
Noriko Hiroi,
Yuichiro Shibata,
Naoki Iwanaga,
Hideki Yamada,
Hiroaki Kitano,
Hideharu Amano:
FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method.
FPL 2007: 254-259 |
| 129 | | Daihan Wang,
Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano:
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.
FPL 2007: 383-388 |
| 128 | | Takamasa Kanamori,
Hideharu Amano,
Masatoshi Arai,
Daisuke Konno,
Tomomichi Nanba,
Yoshiaki Ajioka:
A High Speed License Plate Recognition System on an FPGA.
FPL 2007: 554-557 |
| 127 | | Yohei Hasegawa,
Hideharu Amano:
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays.
FPL 2007: 796-799 |
| 126 | | Hideki Yamada,
Naoki Iwanaga,
Yuichiro Shibata,
Yasunori Osana,
Masato Yoshimi,
Yow Iwaoka,
Yuri Nishikawa,
Toshinori Kojima,
Hideharu Amano,
Akira Funahashi,
Noriko Hiroi,
Hiroaki Kitano,
Kiyoshi Oguri:
A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator.
FPL 2007: 808-811 |
| 125 | | Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano:
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs.
ICPP 2007: 75 |
| 124 | | Yuri Nishikawa,
Michihiro Koibuchi,
Masato Yoshimi,
Kenichi Miura,
Hideharu Amano:
Performance Improvement Methodology for ClearSpeed's CSX600.
ICPP 2007: 77 |
| 123 | | Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano:
Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.
IPDPS 2007: 1-10 |
| 122 | | Atushi Ohta,
Yoshihiro Hamada,
Akira Kitamura,
Noboru Tanabe,
Hideharu Amano,
Hironori Nakajo:
Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.
PDPTA 2007: 787-793 |
| 121 | | Akira Kitamura,
Yasuo Miyabe,
Tomotaka Miyashiro,
Noboru Tanabe,
Hironori Nakajo,
Hideharu Amano:
Performance evaluation on low-latency communication mechanism of DIMMnet-2.
Parallel and Distributed Computing and Networks 2007: 57-62 |
| 120 | | Akiya Jouraku,
Michihiro Koibuchi,
Hideharu Amano:
An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks.
IEEE Trans. Parallel Distrib. Syst. 18(3): 320-333 (2007) |
| 119 | | Konosuke Watanabe,
Tomohiro Otsuka,
Junichiro Tsuchiya,
Hiroaki Nishi,
Junji Yamamoto,
Noboru Tanabe,
Tomohiro Kudoh,
Hideharu Amano:
Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs.
IEEE Trans. Parallel Distrib. Syst. 18(9): 1282-1295 (2007) |
| 118 | | Daihan Wang,
Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano:
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs.
IEICE Transactions 90-D(12): 1914-1922 (2007) |
| 117 | | Vasutan Tunbunheng,
Masayasu Suzuki,
Hideharu Amano:
Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices.
IEICE Transactions 90-D(2): 473-481 (2007) |
| 2006 |
|---|
| 116 | | Vu Manh Tuan,
Yohei Hasegawa,
Naohiro Katsura,
Hideharu Amano:
Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor.
ARC 2006: 115-121 |
| 115 | | Daihan Wang,
Hiroki Matsutani,
Masato Yoshimi,
Michihiro Koibuchi,
Hideharu Amano:
A Parametric Study of Scalable Interconnects on FPGAs.
ERSA 2006: 130-135 |
| 114 | | Hideharu Amano,
Yohei Hasegawa,
Shohei Abe,
K. Ishikawa,
Shunsuke Tsutsumi,
Shunsuke Kurotaki,
Takuro Nakamura,
Takashi Nishimura:
A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.
FPL 2006: 1-6 |
| 113 | | Masato Yoshimi,
Yasunori Osana,
Yow Iwaoka,
Yuri Nishikawa,
Toshinori Kojima,
Akira Funahashi,
Noriko Hiroi,
Yuichiro Shibata,
Naoki Iwanaga,
Hiroaki Kitano,
Hideharu Amano:
An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems.
FPL 2006: 1-6 |
| 112 | | Yasunori Osana,
Masato Yoshimi,
Akira Funahashi,
Noriko Hiroi,
Yuichiro Shibata,
Naoki Iwanaga,
Hiroaki Kitano,
Hideharu Amano:
Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip.
FPL 2006: 1-6 |
| 111 | | Tomohiro Otsuka,
Michihiro Koibuchi,
Tomohiro Kudoh,
Hideharu Amano:
Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet.
ICPP 2006: 479-486 |
| 110 | | Masayasu Suzuki,
Yohei Hasegawa,
Vu Manh Tuan,
Shohei Abe,
Hideharu Amano:
A cost-effective context memory structure for dynamically reconfigurable processors.
IPDPS 2006 |
| 109 | | Yohei Hasegawa,
Shohei Abe,
Shunsuke Kurotaki,
Vu Manh Tuan,
Naohiro Katsura,
Takuro Nakamura,
Takashi Nishimura,
Hideharu Amano:
Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor.
IPDPS 2006 |
| 108 | | Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano:
A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks.
ISCA PDCS 2006: 24-31 |
| 107 | | Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano:
Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels.
ISPA 2006: 207-218 |
| 106 | | Michihiro Koibuchi,
Kenichiro Anjo,
Yutaka Yamada,
Akiya Jouraku,
Hideharu Amano:
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips.
IEEE Trans. Parallel Distrib. Syst. 17(12): 1425-1437 (2006) |
| 105 | | Hideharu Amano:
A Survey on Dynamically Reconfigurable Processors.
IEICE Transactions 89-B(12): 3179-3187 (2006) |
| 2005 |
|---|
| 104 | | Katsuaki Deguchi,
Shohei Abe,
Masayasu Suzuki,
Kenichiro Anjo,
Toru Awashima,
Hideharu Amano:
Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor.
ARCS Workshops 2005: 12-18 |
| 103 | | Hideharu Amano,
Shohei Abe,
Yohei Hasegawa,
Katsuaki Deguchi,
Masayasu Suzuki:
Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor.
FCCM 2005: 315-316 |
| 102 | | Yohei Hasegawa,
Shohei Abe,
Katsuaki Deguchi,
Masayasu Suzuki,
Hideharu Amano:
Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation.
FPGA 2005: 265 |
| 101 | | Hideharu Amano,
Shohei Abe,
Katsuaki Deguchi,
Yohei Hasegawa:
An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration?
FPL 2005: 347-352 |
| 100 | | Yasunori Osana,
Yow Iwaoka,
Tomonori Fukushima,
Masato Yoshimi,
Akira Funahashi,
Noriko Hiroi,
Yuichiro Shibata,
Naoki Iwanaga,
Hiroaki Kitano,
Hideharu Amano:
A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA.
FPL 2005: 574-577 |
| 99 | | Naoki Iwanaga,
Yuichiro Shibata,
Masato Yoshimi,
Yasunori Osana,
Yow Iwaoka,
Tomonori Fukushima,
Hideharu Amano,
Akira Funahashi,
Noriko Hiroi,
Hiroaki Kitano,
Kiyoshi Oguri:
Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA.
FPL 2005: 666-669 |
| 98 | | Vasutan Tunbunheng,
Masayasu Suzuki,
Hideharu Amano:
RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices.
FPT 2005: 129-136 |
| 97 | | Yohei Hasegawa,
Shohei Abe,
Hiroki Matsutani,
Hideharu Amano,
Kenichiro Anjo,
Toru Awashima:
An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor.
FPT 2005: 163-170 |
| 96 | | Masato Yoshimi,
Yasunori Osana,
Yow Iwaoka,
Akira Funahashi,
Noriko Hiroi,
Yuichiro Shibata,
Naoki Iwanaga,
Hiroaki Kitano,
Hideharu Amano:
The Design of Scalable Stochastic Biochemical Simulator on FPGA.
FPT 2005: 339-340 |
| 95 | | Tomohiro Otsuka,
Michihiro Koibuchi,
Akiya Jouraku,
Hideharu Amano:
VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus.
ICPP 2005: 567-576 |
| 94 | | Hiroki Matsutani,
Michihiro Koibuchi,
Yutaka Yamada,
Akiya Jouraku,
Hideharu Amano:
Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips.
ICPP Workshops 2005: 273-280 |
| 93 | | Yasunori Osana,
Tomonori Fukushima,
Masato Yoshimi,
Yow Iwaoka,
Yuichiro Shibata,
Hiroaki Kitano,
Akira Funahashi,
Noriko Hiroi,
Hideharu Amano:
An FPGA-Based, Multi-model Simulation Method for Biochemical Systems.
IPDPS 2005 |
| 92 | | Akira Kitamura,
Yasuo Miyabe,
Tetsu Izawa,
Tomotaka Miyashiro,
Konosuke Watanabe,
Tomohiro Otsuka,
Hideharu Amano,
Yoshihiro Hamada,
Noboru Tanabe,
Hironori Nakajo:
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board.
PDCAT 2005: 778-780 |
| 91 | | Toshihiro Hanawa,
Toshiya Minai,
Yasuki Tanabe,
Hideharu Amano:
Implementation of ISIS-SimpleScalar.
PDPTA 2005: 117-123 |
| 90 | | Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano:
Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips.
PDPTA 2005: 1343-1349 |
| 89 | | Yoshihiro Hamada,
Hiroaki Nishi,
Akira Kitamura,
Noboru Tanabe,
Hideharu Amano,
Hironori Nakajo:
A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.
PDPTA 2005: 461-467 |
| 88 | | Michihiro Koibuchi,
Konosuke Watanabe,
Tomohiro Otsuka,
Hideharu Amano:
Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster.
IEEE Trans. Parallel Distrib. Syst. 16(8): 747-759 (2005) |
| 87 | | Michihiro Koibuchi,
Akiya Jouraku,
Hideharu Amano:
MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing.
IEICE Transactions 88-D(1): 109-118 (2005) |
| 86 | | Michihiro Koibuchi,
Akiya Jouraku,
Hideharu Amano:
Path selection algorithm: the strategy for designing deterministic routing from alternative paths.
Parallel Computing 31(1): 117-130 (2005) |
| 85 | | Takashi Midorikawa,
Daisuke Shiraishi,
Masayoshi Shigeno,
Yasuki Tanabe,
Toshihiro Hanawa,
Hideharu Amano:
The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism).
Parallel Computing 31(3-4): 352-370 (2005) |
| 2004 |
|---|
| 84 | | Yasunori Osana,
Tomonori Fukushima,
Hideharu Amano:
ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA.
ASP-DAC 2004: 731-733 |
| 83 | | Masahiko Kawamura,
Hideharu Amano:
Future reconfigurable computing system.
ASP-DAC 2004: 798 |
| 82 | | Yutaka Yamada,
Hideharu Amano,
Michihiro Koibuchi,
Akiya Jouraku,
Kenichiro Anjo,
Katsunobu Nishimura:
Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array.
EUC 2004: 301-311 |
| 81 | | Noriaki Suzuki,
Shunsuke Kurotaki,
Masayasu Suzuki,
Naoto Kaneko,
Yutaka Yamada,
Katsuaki Deguchi,
Yohei Hasegawa,
Hideharu Amano,
Kenichiro Anjo,
Masato Motomura,
Kazutoshi Wakabayashi,
Takeo Toi,
Toru Awashima:
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
FCCM 2004: 328-329 |
| 80 | | Masato Yoshimi,
Yasunori Osana,
Tomonori Fukushima,
Hideharu Amano:
Stochastic Simulation for Biochemical Reactions on FPGA.
FPL 2004: 105-114 |
| 79 | | Hideharu Amano,
Takeshi Inuo,
Hirokazu Kami,
Taro Fujii,
Masayasu Suzuki:
Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases.
FPL 2004: 464-473 |
| 78 | | Kenichiro Anjo,
Yutaka Yamada,
Michihiro Koibuchi,
Akiya Jouraku,
Hideharu Amano:
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips.
IPDPS 2004 |
| 77 | | Masato Sumiyoshi,
Takashi Midorikawa,
Yasuki Tanabe,
Hideharu Amano:
Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory.
ISCA PDCS 2004: 296-301 |
| 76 | | Noboru Tanabe,
Hironori Nakajo,
Hirotaka Hakozaki,
Masasige Nakatake,
Yasunori Dohi,
Hideharu Amano:
A New Memory Module for Memory Intensive Applications.
PARELEC 2004: 123-128 |
| 2003 |
|---|
| 75 | | Alexander V. Veidenbaum,
Kazuki Joe,
Hideharu Amano,
Hideo Aiso:
High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings
Springer 2003 |
| 74 | | Tomohiro Otsuka,
Konosuke Watanabe,
Junichiro Tsuchiya,
Hiroshi Harada,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Hideharu Amano:
Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System.
Applied Informatics 2003: 738-743 |
| 73 | | Konosuke Watanabe,
Tomohiro Otsuka,
Junichiro Tsuchiya,
Hideharu Amano,
Hiroshi Harada,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh:
Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems.
CCGRID 2003: 318-325 |
| 72 | | Michihiro Koibuchi,
Konosuke Watanabe,
Kenichi Kono,
Akiya Jouraku,
Hideharu Amano:
Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster.
CLUSTER 2003: 395- |
| 71 | | Hideharu Amano,
Akiya Jouraku,
Kenichiro Anjo:
A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device.
FPL 2003: 161-170 |
| 70 | | Toshiro Kitaoka,
Hideharu Amano,
Kenichiro Anjo:
Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device.
FPL 2003: 171-180 |
| 69 | | Yasunori Osana,
Tomonori Fukushima,
Hideharu Amano:
Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform.
FPL 2003: 766-775 |
| 68 | | Michihiro Koibuchi,
Akiya Jouraku,
Konosuke Watanabe,
Hideharu Amano:
Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies.
ICPP 2003: 527- |
| 67 | | Yasuki Tanabe,
Takashi Midorikawa,
Daisuke Shiraishi,
Masayoshi Shigeno,
Toshihiro Hanawa,
Hideharu Amano:
Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism.
PDPTA 2003: 1148-1154 |
| 66 | | Noriaki Suzuki,
Hideharu Amano:
Performance Evaluation of Instruction Set Architecture of MBP-Light: A Distributed Memory Controller for a Large Scale Multiprocessor.
PDPTA 2003: 1155-1164 |
| 2002 |
|---|
| 65 | | Naoto Kaneko,
Hideharu Amano:
A General Hardware Design Model for Multicontext FPGAs.
FPL 2002: 1037-1047 |
| 64 | | Naoyuki Izu,
Tomonori Yokoyama,
Junichiro Tsuchiya,
Konosuke Watanabe,
Hideharu Amano:
RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing.
FPL 2002: 1118-1121 |
| 63 | | Akiya Jouraku,
Michihiro Koibuchi,
Hideharu Amano,
Akira Funahashi:
Routing Algorithms Based on 2D Turn Model for Irregular Networks.
ISPAN 2002: 289-294 |
| 62 | | Noboru Tanabe,
Yoshihiro Hamada,
Hironori Nakajo,
Hideki Imashiro,
Junji Yamamoto,
Tomohiro Kudoh,
Hideharu Amano:
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot.
PARELEC 2002: 9-14 |
| 61 | | Michihiro Koibuchi,
Akiya Jouraku,
Hideharu Amano:
The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing.
PDPTA 2002: 1431-1437 |
| 60 | | Noboru Tanabe,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Yoshihiro Hamada,
Hironori Nakajo,
Hideharu Amano:
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot.
Cluster Computing 5(1): 7-17 (2002) |
| 2001 |
|---|
| 59 | | Daisuke Kawakami,
Yuichiro Shibata,
Hideharu Amano:
A prototype chip of multicontext FPGA with DRAM for virtual hardware.
ASP-DAC 2001: 17-18 |
| 58 | | Akira Funahashi,
Michihiro Koibuchi,
Akiya Jouraku,
Hideharu Amano:
The impact of output selection function on adaptive routing.
Computers and Their Applications 2001: 241-246 |
| 57 | | Michihiro Koibuchi,
Akira Funahashi,
Akiya Jouraku,
Hideharu Amano:
L-Turn Routing: An Adaptive Routing in Irregular Networks.
ICPP 2001: 383-392 |
| 56 | | Michihiro Koibuchi,
Akiya Jouraku,
Akira Funahashi,
Hideharu Amano:
MMLRU Selection Function: An Output Selection Function on Adaptive Routing.
ISCA PDCS 2001: 1-6 |
| 55 | | Yulu Yang,
Akira Funahashi,
Akiya Jouraku,
Hiroaki Nishi,
Hideharu Amano,
Toshinori Sueyoshi:
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
IEEE Trans. Parallel Distrib. Syst. 12(7): 701-715 (2001) |
| 54 | | Hiroaki Nishi,
Koji Tasho,
Tomohiro Kudoh,
Hideharu Amano:
A network switch for supporting high-performance parallel processing by computers distributed in local areas.
Systems and Computers in Japan 32(14): 24-33 (2001) |
| 2000 |
|---|
| 53 | | Takahiro Kawaguchi,
Takayuki Suzuki,
Hideharu Amano:
A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system.
ASP-DAC 2000: 31-32 |
| 52 | | Noboru Tanabe,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Yoshihiro Hamada,
Hironori Nakajo,
Hideharu Amano:
MEMOnet : Network interface plugged into a memory slot.
CLUSTER 2000: 17-16 |
| 51 | | Ou Yamamoto,
Yuichiro Shibata,
Hitoshi Kurosawa,
Hideharu Amano:
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems.
FCCM 2000: 291-294 |
| 50 | | Yuichiro Shibata,
Masaki Uno,
Hideharu Amano,
K. Furuta,
Taro Fujii,
Masato Motomura:
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device.
FCCM 2000: 295-296 |
| 49 | | Ou Yamamoto,
Yuichiro Shibata,
Hitoshi Kurosawa,
Hideharu Amano:
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems.
FPL 2000: 475-484 |
| 48 | | Hideharu Amano,
Yuichiro Shibata,
Masaki Uno:
Reconfigurable Systems: New Activities in Asia.
FPL 2000: 585-594 |
| 47 | | Atsushi Takayama,
Yuichiro Shibata,
Keisuke Iwai,
Hideharu Amano:
Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware.
FPL 2000: 685-694 |
| 46 | | Hiroaki Nishi,
Koji Tasho,
Junji Yamamoto,
Tomohiro Kudoh,
Hideharu Amano:
A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing.
HPDC 2000: 296-297 |
| 45 | | Noboru Tanabe,
Junji Yamamoto,
Hiroaki Nishi,
Tomohiro Kudoh,
Yoshihiro Hamada,
Hironori Nakajo,
Hideharu Amano:
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism.
ISPAN 2000: 186-194 |
| 44 | | Hironori Nakajo,
M. Ishii,
T. Kudo,
Hideharu Amano:
Coherence Protocol for Home Proxy Cache on RHiNET.
PDPTA 2000 |
| 43 | | Shinji Nishimura,
K. Harasawa,
N. Matsudaira,
S. Akutsu,
Tomohiro Kudoh,
Hiroaki Nishi,
Hideharu Amano:
RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection.
New Generation Comput. 18(2): 187- (2000) |
| 1999 |
|---|
| 42 | | Masaki Wakabayashi,
Keisuke Inoue,
Hideharu Amano:
ISIS: Multiprocessor Simulator Library.
Applied Informatics 1999: 198-200 |
| 41 | | Xiaoshe Dong,
Tomohiro Kudoh,
Hideharu Amano:
A Routing Algorithm for DS-WDM Ring.
Applied Informatics 1999: 562-565 |
| 40 | | Takahiro Kawaguchi,
Takashi Fujiwara,
Katsuto Sakamoto,
Keisuke Iwai,
Hideharu Amano:
Floating Point Arithmetic Unit for the Custom Processor Maple.
Applied Informatics 1999: 578-580 |
| 39 | | Atsushi Takayama,
Yuichiro Shibata,
Keisuke Iwai,
Hidenori Miyazaki,
Koichi Higure,
Xiao-ping Ling,
Hideharu Amano:
Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System.
ICPP Workshops 1999: 346-351 |
| 38 | | Yuichiro Shibata,
Xiao-ping Ling,
Hideharu Amano:
Internal Parallelization of Data-Driven Virtual Hardware.
ICPP Workshops 1999: 366- |
| 37 | | Qin Fan,
Yulu Yang,
Akira Funahashi,
Hideharu Amano:
A Torus Assignment for an Interconnection Network Recursive Diagonal Torus.
ISPAN 1999: 74-79 |
| 36 | | Fumiharu Morisawa,
Daisuke Kawakami,
Kensuke Tanaka,
Hideharu Amano:
An Educational System of LSI Design with Free-Wares for VDEC.
MSE 1999: 61-62 |
| 35 | | Junji Yamamoto,
Takashi Fujiwara,
T. Komeda,
Takayuki Kamei,
Toshihiro Hanawa,
Hideharu Amano:
Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture.
Parallel Computing 25(9): 1081-1103 (1999) |
| 1998 |
|---|
| 34 | | Takashi Midorikawa,
Takayuki Kamei,
Toshihiro Hanawa,
Hideharu Amano:
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip.
ASP-DAC 1998: 337-338 |
| 33 | | Hideharu Amano,
Yuichiro Shibata:
Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial).
ASP-DAC 1998: 453-457 |
| 32 | | Yuichiro Shibata,
Hidenori Miyazaki,
Xiao-ping Ling,
Hideharu Amano:
HOSMII: A Virtual Hardware Integrated with DRAM.
IPPS/SPDP Workshops 1998: 85-90 |
| 31 | | Ou Yamamoto,
Takuya Terasawa,
Hideharu Amano:
An analysis of fairness and overhead in the arbitration protocol of the IEEE Futurebus standard.
Systems and Computers in Japan 29(13): 66-77 (1998) |
| 1997 |
|---|
| 30 | | Toru Kisuki,
Masaki Wakabayashi,
Junji Yamamoto,
Keisuke Inoue,
Hideharu Amano:
Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors.
Euro-Par 1997: 793-797 |
| 29 | | Kazumasa Nukata,
Yuichiro Shibata,
Hideharu Amano,
Yuichiro Anzai:
A reconfigurable sensor-data processing system for personal robots.
FPL 1997: 491-500 |
| 28 | | Akira Funahashi,
Toshihiro Hanawa,
Hideharu Amano,
Tomohiro Kudoh:
Adaptive Routing on the Recursive Diagonal Torus.
ISHPC 1997: 171-182 |
| 27 | | Xiaoshe Dong,
Tomohiro Kudoh,
Hideharu Amano:
Wavelength Division Multiple Access Ring - Virtual Topology on a Simple Ring Network.
ISPAN 1997: 30-36 |
| 26 | | Xiao-ping Ling,
Yuichiro Shibata,
Hidenori Miyazaki,
Hideharu Amano,
Koichi Higure:
Total System Image of the Reconfigurable Machine WASMII.
PDPTA 1997: 1092-1096 |
| 25 | | Takuya Terasawa,
Keisuke Inoue,
Hitoshi Kurosawa,
Hideharu Amano:
A study on snoop cache systems for single-chip multiprocessors.
Systems and Computers in Japan 28(2): 62-72 (1997) |
| 1996 |
|---|
| 24 | | Keisuke Inoue,
Toru Kisuki,
Michitaka Okuno,
Etsuko Shimizu,
Takuya Terasawa,
Hideharu Amano:
ATTEMPT-1: A Reconfigurable Multiprocessor Testbed.
FPL 1996: 200-209 |
| 23 | | Yuichiro Shibata,
Xiao-ping Ling,
Hideharu Amano:
An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware.
FPL 1996: 55-64 |
| 1995 |
|---|
| 22 | | Tomohiro Kudoh,
Hideharu Amano,
Takashi Matsumoto,
Kei Hiraki,
Yulu Yang,
Katsunobu Nishimura,
Koichi Yoshimura,
Yasuhito Fukushima:
Hierarchical Bit-Map Directory Schemes on the RDT Interconnection Network for a Massively Parallel Processor JUMP-1.
ICPP (1) 1995: 186-193 |
| 21 | | Junji Yamamoto,
D. Hattori,
Jun-ichi Yamato,
T. Tokuyoshi,
Y. Yamaguchi,
Hideharu Amano:
A Preprocessing System of the EULASH: An Environment for Efficient use of Multiprocessors with Local Memory.
Parallel and Distributed Computing and Systems 1995: 68-71 |
| 20 | | Kyotaro Suzuki,
Hideharu Amano,
Yoshiyasu Takefuji:
Neural network parallel computing for multi-layer channel routing problems.
Neurocomputing 8(2): 141-156 (1995) |
| 19 | | Takuya Terasawa,
Ou Yamamoto,
Tomohiro Kudoh,
Hideharu Amano:
A Performance Evaluation of the Multiprocessor Testbed ATTEMPT-0.
Parallel Computing 21(5): 701-730 (1995) |
| 1994 |
|---|
| 18 | | Xiao-yu Chen,
Xiao-ping Ling,
Hideharu Amano:
Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware.
FPL 1994: 208-219 |
| 17 | | Toshihiro Hanawa,
Hideharu Amano,
Yoshifumi Fujikawa:
Multistage Interconnection Networks with Multiple Outlets.
ICPP (1) 1994: 1-8 |
| 16 | | Masashi Sasahara,
Jun Terada,
Luo Zhou,
Kalidou Gaye,
Jun-ichi Yamato,
Satoshi Ogura,
Hideharu Amano:
SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture.
ICPP (1) 1994: 117-120 |
| 1993 |
|---|
| 15 | | Xiao-ping Ling,
Hideharu Amano:
Performance evaluation of WASMII: a data driven computer on a virtual hardware.
PARLE 1993: 610-621 |
| 14 | | Yulu Yang,
Hideharu Amano,
Hidetomo Shibamura,
Toshinori Sueyoshi:
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers.
SPDP 1993: 591-595 |
| 1992 |
|---|
| 13 | | Tomohiro Kudoh,
Tetsuro Kimura,
Hideharu Amano,
Takuya Terasawa:
A Parallel Logic Simulation Algorithm Based on Query.
ICPP (3) 1992: 262-266 |
| 12 | | Hideharu Amano,
Luo Zhou,
Kalidou Gaye:
SSS (Simple Serial Synchronized)-MIN: A Novel Multi Stage Interconnection Architecture for Multiprocessors.
IFIP Congress (1) 1992: 571-577 |
| 1991 |
|---|
| 11 | | Hideharu Amano,
Kalidou Gaye:
A Batcher Double Omega Network with Combining.
ICPP (1) 1991: 718-719 |
| 1990 |
|---|
| 10 | | Hideharu Amano:
A Fault Tolerant Batcher Network.
ICPP (1) 1990: 441-444 |
| 9 | | Hideharu Amano,
Taisuke Boku,
Tomohiro Kudoh:
(SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations.
IEEE Trans. Computers 39(7): 889-905 (1990) |
| 1989 |
|---|
| 8 | | Hideharu Amano,
Takuya Terasawa,
Tomohiro Kudoh:
Cache with Synchronization Mechanism.
IFIP Congress 1989: 1001-1006 |
| 7 | | Jun Miyazaki,
Kenji Takeda,
Hideharu Amano,
Hideo Aiso:
A New Version of a Parallel Production System Machine, MANJI-II.
IWDM 1989: 317-330 |
| 6 | | Xiao-ping Ling,
Hideharu Amano:
A static scheduling system for a parallel machine (SM)2-II.
PARLE (1) 1989: 118-135 |
| 1988 |
|---|
| 5 | | Taisuke Boku,
Shigehiro Nomura,
Hideharu Amano:
IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation.
ISCA 1988: 365-372 |
| 1987 |
|---|
| 4 | | Jun Miyazaki,
Hideharu Amano,
Kenji Takeda,
Hideo Aiso:
A Shared Memory Architecture for MANJI Production System Machine.
IWDM 1987: 517-531 |
| 1986 |
|---|
| 3 | | Chizuko Saito,
Hideharu Amano,
Tomohiro Kudoh,
Hideo Aiso:
An Adaptable Cluster Structure of (SM)²-II.
CONPAR 1986: 53-60 |
| 1985 |
|---|
| 2 | | Hideharu Amano,
Taisuke Boku,
Tomohiro Kudoh,
Hideo Aiso:
(SM)²-II: A New Version of the Sparse Matrix Solving Machine.
ISCA 1985: 100-107 |
| 1983 |
|---|
| 1 | | Hideharu Amano,
Takaichi Yoshida,
Hideo Aiso:
(SM)2: Sparse Matrix Solving Machine
ISCA 1983: 213-220 |
