Yoshihito Amemiya

	2009
26		Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC 2009: 95-96
25		Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya: Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution. NanoNet 2009: 51-56
24		Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Transactions 92-A(2): 436-442 (2009)
	2008
23		Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya: Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. ICONIP (2) 2008: 851-858
22		Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Transactions 91-A(9): 2475-2481 (2008)
	2007
21		Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) 2007: 117-126
20		Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN 2007: 897-901
19		Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS 2007: 3748-3751
18		Andrew Kilinga Kikombo, Takahide Oya, Tetsuya Asai, Yoshihito Amemiya: Discrete Dynamical Systems Consisting of Single-electron Circuits. I. J. Bifurcation and Chaos 17(10): 3613-3617 (2007)
17		Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. I. J. Bifurcation and Chaos 17(5): 1713-1719 (2007)
16		Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Transactions 90-A(10): 2108-2115 (2007)
15		Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya: A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing 71(1-3): 3-12 (2007)
	2006
14		Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya: A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. I. J. Bifurcation and Chaos 16(1): 207-212 (2006)
13		Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Transactions 89-A(4): 902-907 (2006)
12		Yoshihito Amemiya: Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions. IEICE Transactions 89-C(11): 1504-1511 (2006)
	2005
11		Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya: Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. ISCAS (3) 2005: 1923-1926
10		Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici: Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. ISCAS (3) 2005: 2535-2538
9		Takahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya: On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electronic Express 2(3): 76-80 (2005)
8		Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya: Ultralow-Power Current Reference Circuit with Low Temperature Dependence. IEICE Transactions 88-C(6): 1142-1147 (2005)
7		Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya: A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. 20(1): 57-67 (2005)
	2004
6		Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya: An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. ISCAS (3) 2004: 1-4
5		Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electronic Express 1(4): 73-76 (2004)
4		Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. IEICE Electronic Express 1(9): 248-252 (2004)
	2003
3		Tetsuya Asai, Yoshihito Amemiya: Biomorphic Analog Devices based on Reaction-Diffusion Systems. ISMVL 2003: 197-
	2000
2		Tetsuya Asai, Masato Koutani, Yoshihito Amemiya: An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. IJCNN (3) 2000: 494-499
	1998
1		Masayuki Ikebe, Masamichi Akazawa, Yoshihito Amemiya: nu-MOS cellular-automaton devices for intelligent image sensors. KES (3) 1998: 447-453

Coauthor Index

1	Masamichi Akazawa	[1]
2	Tetsuya Asai	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26]
3	Eric Shun Fukuda	[20] [21]
4	Hatsuo Hayashi	[15]
5	Tetsuya Hirose	[4] [5] [7] [8] [13] [14] [15] [16] [17] [19] [20] [21] [22] [24] [26]
6	Masayuki Ikebe	[1] [7]
7	Taishi Kamiya	[14]
8	Yusuke Kanazawa	[5]
9	Andrew Kilinga Kikombo	[18] [25]
10	Masato Koutani	[2]
11	Yusuf Leblebici	[9] [10]
12	Hiroshi Matsubara	[4]
13	Toshimasa Matsuoka	[8]
14	Kazuki Nakada	[6] [11] [15]
15	Taichi Ogawa	[24]
16	Takahide Oya	[9] [10] [18]
17	Alexandre Schmid	[9] [10]
18	Motoyoshi Takahashi	[17]
19	Kenji Taniguchi	[8]
20	Gessyca Maria Tovar	[20] [21] [23]
21	Ken Ueno	[13] [19] [26]
22	Akira Utagawa	[16] [22]