 | 2008 |
|---|
| 9 |       | Érika F. Cota,
Fernanda Gusmão de Lima Kastensmidt,
Maico Cassel,
Marcos Herve,
Pedro Almeida,
Paulo Meirelles,
Alexandre M. Amory,
Marcelo Lubaszewski:
A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.
IEEE Trans. Computers 57(9): 1202-1215 (2008) |
| 2007 |
|---|
| 8 | | Alexandre M. Amory,
Frederico Ferlini,
Marcelo Lubaszewski,
Fernando Moraes:
DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.
VTS 2007: 435-440 |
| 7 | | Alexandre M. Amory,
Marcelo Lubaszewski,
Fernando Gehm Moraes,
Edson I. Moreno:
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
CoRR abs/0710.4795: (2007) |
| 2006 |
|---|
| 6 | | Alexandre M. Amory,
Kees Goossens,
Erik Jan Marinissen,
Marcelo Lubaszewski,
Fernando Moraes:
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.
European Test Symposium 2006: 213-218 |
| 2005 |
|---|
| 5 | | Alexandre M. Amory,
Marcelo Lubaszewski,
Fernando Gehm Moraes,
Edson I. Moreno:
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.
DATE 2005: 62-63 |
| 2004 |
|---|
| 4 | | Alexandre M. Amory,
Érika F. Cota,
Marcelo Lubaszewski,
Fernando Gehm Moraes:
Reducing test time with processor reuse in network-on-chip based systems.
SBCCI 2004: 111-116 |
| 2003 |
|---|
| 3 |  | Alexandre M. Amory,
Leandro A. Oliveira,
Fernando Gehm Moraes:
Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures.
VLSI-SOC 2003: 174-179 |
| 2000 |
|---|
| 2 | | Fabian Vargas,
Alexandre M. Amory:
Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis.
Asian Test Symposium 2000: 417-422 |
| 1 | | Fabian Vargas,
Alexandre M. Amory,
Raoul Velazco:
Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL.
IOLTW 2000: 67-72 |
