Nazrul Anuar

Nazrul Anuar Nayan

	2012
3		Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine: LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. Microelectronics Journal 43(4): 244-249 (2012)
	2010
2		Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine: 4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. VLSI-SoC 2010: 364-368
	2009
1		Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine: Fundamental logics based on two phase clocked adiabatic static CMOS logic. ICECS 2009: 503-506

Coauthor Index

1	Toshikazu Sekine	[1] [2] [3]
2	Yasuhiro Takahashi	[1] [2] [3]

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