Chatchawit Aporntewan

	2007
7		Chatchawit Aporntewan, Prabhas Chongstitvatana: Building-block Identification by Simultaneity Matrix. Soft Comput. 11(6): 541-548 (2007)
	2005
6		Chatchawit Aporntewan, Prabhas Chongstitvatana: A quantitative approach for validating the building-block hypothesis. Congress on Evolutionary Computation 2005: 1403-1409
	2004
5		Chatchawit Aporntewan, Prabhas Chongstitvatana: Chi-Square Matrix: An Approach for Building-Block Identification. ASIAN 2004: 63-77
4		Chatchawit Aporntewan, Prabhas Chongstitvatana: Simultaneity Matrix for Solving Hierarchically Decomposable Functions. GECCO (1) 2004: 877-888
	2003
3		Chatchawit Aporntewan, Prabhas Chongstitvatana: Building-Block Identification by Simultaneity Matrix. GECCO 2003: 1566-1567
	1999
2		Prabhas Chongstitvatana, Chatchawit Aporntewan: Improving Correctness of Finite-State Machine Synthesis from Multiple Partial Input/Output Sequences. Evolvable Hardware 1999: 262-
	1998
1		Chaiyasit Manovit, Chatchawit Aporntewan, Prabhas Chongstitvatana: Synthesis of Synchronous Sequential Logic Circuits from Partial Input/Output Sequences. ICES 1998: 98-105

Coauthor Index

1	Prabhas Chongstitvatana	[1] [2] [3] [4] [5] [6] [7]
2	Chaiyasit Manovit	[1]