Juan L. Aragón

	2009
17		Daniel Sánchez, Juan L. Aragón, José M. García: REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs. Euro-Par 2009: 321-333
16		Juan M. Cebrian, Juan L. Aragón, José M. García, Pavlos Petoumenos, Stefanos Kaxiras: Efficient microarchitecture policies for accurately adapting to power constraints. IPDPS 2009: 1-12
15		Daniel Sánchez, Juan L. Aragón, José M. García: Extending SRT for parallel applications in tiled-CMP architectures. IPDPS 2009: 1-8
	2008
14		Antonio Flores, Manuel E. Acacio, Juan L. Aragón: Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. ICPP 2008: 295-303
13		Juan L. Aragón, Alexander V. Veidenbaum: Optimizing CAM-based instruction cache designs for low-power embedded systems. Journal of Systems Architecture - Embedded Systems Design 54(12): 1155-1163 (2008)
12		Antonio Flores, Juan L. Aragón, Manuel E. Acacio: An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. The Journal of Supercomputing 45(3): 341-364 (2008)
	2007
11		Antonio Flores, Juan L. Aragón, Manuel E. Acacio: Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. AINA Workshops (1) 2007: 752-757
10		Juan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras: Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors. Conf. Computing Frontiers 2007: 113-122
9		Antonio Flores, Juan L. Aragón, Manuel E. Acacio: Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. HiPC 2007: 133-146
8		Juan M. Cebrian, Juan L. Aragón, José M. García: Leakage Energy Reduction in Value Predictors through Static Decay. IPDPS 2007: 1-7
	2006
7		Juan L. Aragón, José M. González, Antonio González: Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. IEEE Trans. Computers 55(3): 281-291 (2006)
	2005
6		Juan L. Aragón, Alexander V. Veidenbaum: Energy-Effective Instruction Fetch Unit for Wide Issue Processors. Asia-Pacific Computer Systems Architecture Conference 2005: 15-27
	2004
5		Juan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu: Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. DATE 2004: 1374-1375
	2003
4		Juan L. Aragón, José González, Antonio González: Power-Aware Control Speculation through Selective Throttling. HPCA 2003: 103-112
	2002
3		Juan L. Aragón, José González, Antonio González, James E. Smith: Dual path instruction processing. ICS 2002: 220-229
	2001
2		Juan L. Aragón, José González, José M. García, Antonio González: Confidence Estimation for Branch Prediction Reversal. HiPC 2001: 214-223
1		Juan L. Aragón, José González, José M. García, Antonio González: Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. ICCD 2001: 228-233

Coauthor Index

1	Manuel E. Acacio	[9] [11] [12] [14]
2	Ana-Maria Badulescu	[5]
3	Juan M. Cebrian	[8] [10] [16]
4	Antonio Flores	[9] [11] [12] [14]
5	José M. García	[1] [2] [8] [10] [15] [16] [17]
6	Antonio González	[1] [2] [3] [4] [7]
7	José González	[1] [2] [3] [4]
8	José M. González	[7]
9	Stefanos Kaxiras	[10] [16]
10	Dan Nicolaescu	[5]
11	Pavlos Petoumenos	[16]
12	Daniel Sánchez	[15] [17]
13	James E. Smith	[3]
14	Alexander V. Veidenbaum	[5] [6] [13]

Colors in the list of coauthors