Hossein Asadi

Ghazanfar Asadi

	2007
17		Hossein Asadi, Mehdi Baradaran Tahoori, Chandra Tirumurti: Estimating Error Propagation Probabilities with Bounded Variances. DFT 2007: 41-49
16		Brian Mullins, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli, Kevin Granlund, Rudy Bauer, Scott Romano: Case Study: Soft Error Rate Analysis in Storage Systems. VTS 2007: 256-264
15		Ghazanfar Asadi, Mehdi Baradaran Tahoori: An Accurate SER Estimation Method Based on Propagation Probability CoRR abs/0710.4712: (2007)
14		Hossein Asadi, Mehdi Baradaran Tahoori: Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs. IEEE Trans. VLSI Syst. 15(12): 1320-1331 (2007)
	2006
13		Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli: Vulnerability analysis of L2 cache elements to single event upsets. DATE 2006: 1276-1281
12		Hossein Asadi, Mehdi Baradaran Tahoori: Soft error derating computation in sequential circuits. ICCAD 2006: 497-501
11		Hossein Asadi, Mehdi Baradaran Tahoori: Soft error hardening for logic-level designs. ISCAS 2006
10		Vilas Sridharan, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli: Reducing Data Cache Susceptibility to Soft Errors. IEEE Trans. Dependable Sec. Comput. 3(4): 353-364 (2006)
	2005
9		Ghazanfar Asadi, Mehdi Baradaran Tahoori: An Accurate SER Estimation Method Based on Propagation Probability. DATE 2005: 306-307
8		Hossein Asadi, Mehdi Baradaran Tahoori: Soft Error Modeling and Protection for Sequential Elements. DFT 2005: 463-474
7		Ghazanfar Asadi, Mehdi Baradaran Tahoori: Soft error rate estimation and mitigation for SRAM-based FPGAs. FPGA 2005: 149-160
6		Ghazanfar Asadi, Mehdi Baradaran Tahoori: An analytical approach for soft error rate estimation in digital circuits. ISCAS (3) 2005: 2991-2994
5		Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli: Balancing Performance and Reliability in the Memory Hierarchy. ISPASS 2005: 269-279
4		Ghazanfar Asadi, Mehdi Baradaran Tahoori: Soft Error Mitigation for SRAM-Based FPGAs. VTS 2005: 207-212
	2004
3		Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali: Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. PRDC 2004: 327-332
	2003
2		Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi: A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. DSN 2003: 479-
	2002
1		Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali: Fast Prototyping with Co-operation of Simulation and Emulation. FPL 2002: 15-25

Coauthor Index

1	Rudy Bauer	[16]
2	Alireza Ejlali (Ali Reza Ejlali)	[1] [2] [3]
3	Kevin Granlund	[16]
4	David R. Kaeli	[5] [10] [13] [16]
5	Seyed Ghassem Miremadi	[1] [2] [3]
6	Brian Mullins	[16]
7	Scott Romano	[16]
8	Siavash Bayat Sarmadi	[1] [2]
9	Vilas Sridharan	[5] [10] [13]
10	Mehdi Baradaran Tahoori	[4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
11	Chandra Tirumurti	[17]
12	Hamid R. Zarandi	[2] [3]

Colors in the list of coauthors