 | 2008 |
|---|
| 8 |       | Maryam Ashouei,
Adit D. Singh,
Abhijit Chatterjee:
Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS.
VLSI Design 2008: 27-32 |
| 2007 |
|---|
| 7 | | Muhammad Mudassar Nisar,
Maryam Ashouei,
Abhijit Chatterjee:
Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums.
IOLTS 2007: 173-182 |
| 6 | | Maryam Ashouei,
Muhammad Mudassar Nisar,
Abhijit Chatterjee,
Adit D. Singh,
Abdulkadir Utku Diril:
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations.
VLSI Design 2007: 711-716 |
| 5 | | Maryam Ashouei,
Soumendu Bhattacharya,
Abhijit Chatterjee:
Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors.
VTS 2007: 125-130 |
| 2006 |
|---|
| 4 | | Maryam Ashouei,
Soumendu Bhattacharya,
Abhijit Chatterjee:
Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study.
European Test Symposium 2006: 35-42 |
| 3 | | Maryam Ashouei,
Abhijit Chatterjee,
Adit D. Singh,
Vivek De,
T. M. Mak:
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design.
VLSI Design 2006: 606-612 |
| 2 | | Maryam Ashouei,
Soumendu Bhattacharya,
Abhijit Chatterjee:
Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error Correction.
VTS 2006: 208-213 |
| 2005 |
|---|
| 1 | | Maryam Ashouei,
Abhijit Chatterjee,
Adit D. Singh,
Vivek De:
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.
ICCD 2005: 567-573 |
