| 2009 | ||
|---|---|---|
| 79 | Stephen Bijansky, Sae Kyu Lee, Adnan Aziz: TuneLogic: Post-silicon tuning of dual-Vdd designs. ISQED 2009: 394-400 | |
| 2008 | ||
| 78 | Stephen Bijansky, Adnan Aziz: TuneFPGA: post-silicon tuning of dual-Vdd FPGAs. DAC 2008: 796-799 | |
| 77 | Jason Baumgartner, Hari Mony, Adnan Aziz: Optimal Constraint-Preserving Netlist Simplification. FMCAD 2008: 1-9 | |
| 76 | Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham: Adaptive SRAM memory for low power and high yield. ICCD 2008: 176-181 | |
| 75 | Amit Prakash, Adnan Aziz: Binary Decision Graph. Encyclopedia of Algorithms 2008 | |
| 74 | Amit Prakash, Adnan Aziz: Symbolic Model Checking. Encyclopedia of Algorithms 2008 | |
| 2007 | ||
| 73 | Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid: Sequential circuits for program analysis. ASE 2007: 114-123 | |
| 72 | Fadi A. Zaraket, John Pape, Adnan Aziz, Margarida F. Jacome, Sarfraz Khurshid: Global Optimization of Compositional Systems. FMCAD 2007: 93-100 | |
| 71 | Hani Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.: Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. ICCD 2007: 7-12 | |
| 70 | Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid: Sequential Circuits for Relational Analysis. ICSE 2007: 13-22 | |
| 69 | Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud: Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations. ISQED 2007: 873-878 | |
| 68 | Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud: Implementing DSP Algorithms with On-Chip Networks. NOCS 2007: 307-316 | |
| 67 | Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.: The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. VLSI-SoC 2007: 194-199 | |
| 66 | Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky: Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies CoRR abs/cs/0703102: (2007) | |
| 2005 | ||
| 65 | Hari Mony, Jason Baumgartner, Adnan Aziz: Exploiting Constraints in Transformation-Based Verification. CHARME 2005: 269-284 | |
| 64 | Fadi A. Zaraket, Jason Baumgartner, Adnan Aziz: Scalable compositional minimization via static analysis. ICCAD 2005: 1060-1067 | |
| 2004 | ||
| 63 | Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Wayne Wolf: Synthesizing interconnect-efficient low density parity check codes. DAC 2004: 488-491 | |
| 62 | Amit Prakash, Adnan Aziz, Vijaya Ramachandran: Randomized Parallel Schedulers for Switch-Memory-Switch Routers: Analysis and Numerical Studies. INFOCOM 2004 | |
| 61 | Jun Yuan, Adnan Aziz, Carl Pixley, Ken Albin: Simplifying Boolean constraint solving for random simulation-vector generation. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 412-420 (2004) | |
| 2003 | ||
| 60 | Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley: Constraint synthesis for environment modeling in functional verification. DAC 2003: 296-299 | |
| 59 | Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin: A Framework for Constrained Functional Verification. ICCAD 2003: 142-145 | |
| 58 | Adnan Aziz, Amit Prakash, Vijaya Ramachandran: A near optimal scheduler for switch-memory-switch routers. SPAA 2003: 343-352 | |
| 57 | Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton: Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. 8(2): 222-251 (2003) | |
| 56 | Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal: BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. Formal Methods in System Design 22(3): 205-224 (2003) | |
| 55 | Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz: An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists. Formal Methods in System Design 23(1): 39-65 (2003) | |
| 54 | Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz: A high-performance architecture and BDD-based synthesis methodology for packet classification. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 698-709 (2003) | |
| 2002 | ||
| 53 | Shashank Gupta, Adnan Aziz: Multicast Scheduling for Switches with Multiple Input-Queues. Hot Interconnects 2002: 28-36 | |
| 52 | Amit Prakash, Adnan Aziz: A Middle Ground between CAMs and DAGs for High-Speed Packet Classification. Hot Interconnects 2002: 89-94 | |
| 51 | Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley: Simplifying Boolean constraint solving for random simulation-vector generation. ICCAD 2002: 123-127 | |
| 50 | Sadia Sharif, Adnan Aziz, Amit Prakash: An O(log2N) parallel algorithm for output queuing. INFOCOM 2002 | |
| 49 | Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley: Simplifying Constraint Solving in Random Simulation Generation. IWLS 2002: 185-190 | |
| 48 | Jun Yuan, Kurt Shultz, John Havlicek, Ken Albin, Adnan Aziz: A Method for Synthesizing Boolean Constrains. IWLS 2002: 351-353 | |
| 47 | Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz: A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification. IWLS 2002: 97-102 | |
| 46 | Malay K. Ganai, Adnan Aziz: Improved SAT-Based Bounded Reachability Analysis. VLSI Design 2002: 729-734 | |
| 45 | Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Formula-Dependent Equivalence for Compositional CTL Model Checking. Formal Methods in System Design 21(2): 193-224 (2002) | |
| 2001 | ||
| 44 | Malay K. Ganai, Adnan Aziz: Rarity based guided state space search. ACM Great Lakes Symposium on VLSI 2001: 97-102 | |
| 43 | I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong: Integrated power supply planning and floorplanning. ASP-DAC 2001: 589-594 | |
| 42 | Tai-Hung Liu, Adnan Aziz, Vigyan Singhal: Optimizing designs containing black boxes. ACM Trans. Design Autom. Electr. Syst. 6(4): 591-601 (2001) | |
| 41 | Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton: Theory of safe replacements for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 249-265 (2001) | |
| 40 | Adnan Aziz, James H. Kukula, Thomas R. Shiple, Jun Yuan: Efficient control state-space search. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 332-336 (2001) | |
| 39 | Hai Zhou, Adnan Aziz: Buffer minimization in pass transistor logic. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 693-697 (2001) | |
| 38 | Malay K. Ganai, Praveen Yalagandula, Adnan Aziz, Andreas Kuehlmann, Vigyan Singhal: SIVA: A System for Coverage-Directed State Space Search. J. Electronic Testing 17(1): 11-27 (2001) | |
| 2000 | ||
| 37 | Jason Baumgartner, Anson Tripp, Adnan Aziz, Vigyan Singhal, Flemming Andersen: An Abstraction Algorithm for the Verification of Generalized C-Slow Designs. CAV 2000: 5-19 | |
| 36 | Praveen Yalagandula, Adnan Aziz, Vigyan Singhal: Automatic Lighthouse Generation for Directed State Space Search. DATE 2000: 237-242 | |
| 35 | I-Min Liu, Adnan Aziz, D. F. Wong: Meeting Delay Constraints in DSM by Minimal Repeater Insertion. DATE 2000: 436-440 | |
| 34 | I-Min Liu, Adnan Aziz: Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. ICCD 2000: 209-214 | |
| 33 | Hai Zhou, Adnan Aziz: Buffer minimization in pass transistor logic. ISPD 2000: 105-110 | |
| 32 | I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong: Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. ISPD 2000: 33-38 | |
| 31 | Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton: Model-checking continous-time Markov chains. ACM Trans. Comput. Log. 1(1): 162-170 (2000) | |
| 30 | Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential synthesis using S1S. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1149-1162 (2000) | |
| 29 | Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 819-824 (2000) | |
| 28 | Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz: Automatic Vector Generation Using Constraints and Biasing. J. Electronic Testing 16(1-2): 107-120 (2000) | |
| 1999 | ||
| 27 | Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz: Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists. CAV 1999: 72-83 | |
| 26 | Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann: Enhancing Simulation with BDDs and ATPG. DAC 1999: 385-390 | |
| 25 | Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC 1999: 96-99 | |
| 24 | Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz: Modeling design constraints and biasing in simulation using BDDs. ICCAD 1999: 584-590 | |
| 23 | I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou: An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD 1999: 210-215 | |
| 22 | Srivatsan Srinivasan, Parminder Singh Chhabra, Praveen Kumar Jaini, Adnan Aziz, Lizy Kurian John: Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking. VLSI Design 1999: 288-293 | |
| 21 | Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns: Performance Driven Synthesis for Pass-Transistor Logic. VLSI Design 1999: 372-377 | |
| 1998 | ||
| 20 | Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal: BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. CAV 1998: 244-255 | |
| 19 | Adnan Aziz, James H. Kukula, Thomas R. Shiple: Hybrid Verification Using Saturated Simulation. DAC 1998: 615-618 | |
| 18 | Yufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz: Hybrid Techniques for Fast Functional Simulation. DAC 1998: 664-667 | |
| 17 | James H. Kukula, Thomas R. Shiple, Adnan Aziz: Techniques for Implicit State Enumeration of EFSMs. FMCAD 1998: 469-482 | |
| 1997 | ||
| 16 | Jun Yuan, Jian Shen, Jacob A. Abraham, Adnan Aziz: On Combining Formal and Informal Verification. CAV 1997: 376-387 | |
| 15 | Tai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal: Optimizing Designs Containing Black Boxes. DAC 1997: 113-116 | |
| 14 | Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli: Sequential optimisation without state space exploration. ICCAD 1997: 208-215 | |
| 1996 | ||
| 13 | Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton: Verifying Continuous Time Markov Chains. CAV 1996: 269-276 | |
| 12 | Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS: A System for Verification and Synthesis. CAV 1996: 428-432 | |
| 11 | Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS. FMCAD 1996: 248-256 | |
| 1995 | ||
| 10 | Adnan Aziz, Vigyan Singhal, Felice Balarin: It Usually Works: The Temporal Logic of Stochastic Systems. CAV 1995: 155-165 | |
| 9 | Adnan Aziz, Felice Balarin, Robert K. Brayton, M. D. DiBenedetto, Alexander Saldanha: Supervisory Control of Finite State Machines. CAV 1995: 279-292 | |
| 8 | Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton: Exploiting power-up delay for sequential optimization. EURO-DAC 1995: 54-59 | |
| 7 | Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Sequential synthesis using S1S. ICCAD 1995: 612-617 | |
| 1994 | ||
| 6 | Adnan Aziz, Thomas R. Shiple, Vigyan Singhal: Formula-Dependent Equivalence for Compositional CTL Model Checking. CAV 1994: 324-337 | |
| 5 | Adnan Aziz, Serdar Tasiran, Robert K. Brayton: BDD Variable Ordering for Interacting Finite State Machines. DAC 1994: 283-288 | |
| 4 | Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459 | |
| 3 | Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Equivalences for Fair Kripke Structures. ICALP 1994: 364-375 | |
| 2 | Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton: Multi-level synthesis for safe replaceability. ICCAD 1994: 442-449 | |
| 1 | Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton: Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. ICCD 1994: 255-261 | |