Navid Azizi

	2007
11		Khaled R. Heloue, Navid Azizi, Farid N. Najm: Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. DAC 2007: 93-98
10		Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm: Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. IEEE Trans. VLSI Syst. 15(7): 746-757 (2007)
	2006
9		Georges Nabaa, Navid Azizi, Farid N. Najm: An adaptive FPGA architecture with process variation compensation and reduced leakage. DAC 2006: 624-629
8		Navid Azizi, Farid N. Najm: A family of cells to reduce the soft-error-rate in ternary-CAM. DAC 2006: 779-784
	2005
7		Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm: Variations-aware low-power design with voltage scaling. DAC 2005: 529-534
6		Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi: A Case for Asymmetric-Cell Cache Memories. IEEE Trans. VLSI Syst. 13(7): 877-881 (2005)
	2004
5		Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow: Reconfigurable Molecular Dynamics Simulator. FCCM 2004: 197-206
4		Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow: FPGA-based supercomputing: an implementation for molecular dynamics. FPGA 2004: 253
3		Navid Azizi, Farid N. Najm: An Asymmetric SRAM Cell to Lower Gate Leakage. ISQED 2004: 534-539
	2003
2		Navid Azizi, Farid N. Najm, Andreas Moshovos: Low-leakage asymmetric-cell SRAM. IEEE Trans. VLSI Syst. 11(4): 701-715 (2003)
	2002
1		Navid Azizi, Andreas Moshovos, Farid N. Najm: Low-leakage asymmetric-cell SRAM. ISLPED 2002: 48-51

Coauthor Index

1	Paul Chow	[4] [5]
2	Ahmad Darabiha	[4] [5]
3	Vivek De	[7] [10]
4	Aaron Egier	[4] [5]
5	Babak Falsafi	[6]
6	Khaled R. Heloue	[11]
7	Muhammad M. Khellah	[7] [10]
8	Ian Kuon	[4] [5]
9	Andreas Moshovos	[1] [2] [6]
10	Georges Nabaa	[9]
11	Farid N. Najm	[1] [2] [3] [6] [7] [8] [9] [10] [11]

Colors in the list of coauthors