 | 2009 |
|---|
| 8 |       | Wolfgang Haid,
Lars Schor,
Kai Huang,
Iuliana Bacivarov,
Lothar Thiele:
Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs.
ESTImedia 2009: 35-44 |
| 7 | | Kai Huang,
Iuliana Bacivarov,
Jun Liu,
Wolfgang Haid:
A modular fast simulation framework for stream-oriented MPSoC.
SIES 2009: 74-81 |
| 2008 |
|---|
| 6 | | Kai Huang,
Iuliana Bacivarov,
Fabian Hugelshofer,
Lothar Thiele:
Scalably distributed SystemC simulation for embedded applications.
SIES 2008: 271-274 |
| 2007 |
|---|
| 5 | | Lothar Thiele,
Iuliana Bacivarov,
Wolfgang Haid,
Kai Huang:
Mapping Applications to Tiled Multiprocessor Embedded Systems.
ACSD 2007: 29-40 |
| 2006 |
|---|
| 4 | | Florin Dumitrascu,
Iuliana Bacivarov,
Lorenzo Pieralisi,
Marius Bonaciu,
Ahmed Amine Jerraya:
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application.
DATE Designers' Forum 2006: 166-171 |
| 2005 |
|---|
| 3 | | Aimen Bouchhima,
Iuliana Bacivarov,
Wassim Youssef,
Marius Bonaciu,
Ahmed Amine Jerraya:
Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration.
ASP-DAC 2005: 969-972 |
| 2 | | Iuliana Bacivarov,
Aimen Bouchhima,
Sungjoo Yoo,
Ahmed Amine Jerraya:
ChronoSym: a new approach for fast and accurate SoC cosimulation.
IJES 1(1/2): 103-111 (2005) |
| 2003 |
|---|
| 1 | | Sungjoo Yoo,
Iuliana Bacivarov,
Aimen Bouchhima,
Yanick Paviot,
Ahmed Amine Jerraya:
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer.
DATE 2003: 10550-10555 |
