John Bainbridge

2008
9	EE	Luis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu: An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. NOCS 2008: 215-216
2007
8	EE	Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley: Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. ASYNC 2007: 60-72
2005
7	EE	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards: Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. VLSI Syst. 13(12): 1384-1393 (2005)
2004
6	EE	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards: Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium 2004: 20-23
5	EE	Stephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple: Sparse distributed memory using N-of-M codes. Neural Networks 17(10): 1437-1451 (2004)
2002
4	EE	John Bainbridge, Stephen B. Furber: Chain: A Delay-Insensitive Chip Area Interconnect. IEEE Micro 22(5): 16-23 (2002)
1994
3		John Bainbridge: Defining Testability Metrics Axiomatically. Softw. Test., Verif. Reliab. 4(2): 63-80 (1994)
1992
2		John Bainbridge: A Heuristic Method for Generating Large Random Expressions. Inf. Process. Lett. 44(3): 165-170 (1992)
1990
1		John Bainbridge, R. W. Whitty, John Wordsworth: Obtaining Structural Metrics of Z Specifications for Systems Development. Z User Workshop 1990: 269-281

Coauthor Index

1	Andrew Bardsley	[8]
2	J. Mike Cumpstey	[5]
3	Douglas A. Edwards	[6] [7]
4	Aristides Efthymiou	[6] [7]
5	Stephen B. Furber	[4] [5]
6	Steve Furber	[9]
7	Jin-Jer Hwan	[8]
8	David L. Jackson	[8]
9	John R. Mawer	[8]
10	Luis A. Plana	[9]
11	Marly Roncken	[8]
12	Sean Salisbury	[9]
13	Mark E. Schuelein	[8]
14	Andrew M. Scott	[8]
15	Yebin Shi	[9]
16	Steve Temple	[5]
17	Robin W. Whitty (R. W. Whitty)	[1]
18	John Wordsworth	[1]
19	Jian Wu	[9]

Colors in the list of coauthors