Artur Balasinski

	2006
5		Artur Balasinski: Question: DRC or DfM ? Answer: FMEA and ROI. ISQED 2006: 789-794
	2005
4		Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Sebastian Magierowski, Rafal Dlugosz, A. Dabrowski: 3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection. ISCAS (2) 2005: 1154-1157
3		Artur Balasinski: DfM for SoC, invited. IWSOC 2005: 41-46
	2004
2		Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Marek Syrzycki: Design Strategies for ESD Protection in SOC. IWSOC 2004: 210-214
	2000
1		Valery Axelrad, Nicolas B. Cobb, M. O'Brien, Thuy Do, Tom Donnelly, Yuri Granik, Emile Y. Sahouria, Victor Boksha, Artur Balasinski: Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs. ISQED 2000: 461-466

Coauthor Index

1	Valery Axelrad	[1] [2] [4]
2	Victor Boksha	[1]
3	Nicolas B. Cobb	[1]
4	A. Dabrowski	[4]
5	Rafal Dlugosz	[4]
6	Thuy Do	[1]
7	Tom Donnelly	[1]
8	Yuri Granik	[1]
9	Krzysztof Iniewski (Kris Iniewski)	[2] [4]
10	Sebastian Magierowski	[4]
11	M. O'Brien	[1]
12	Emile Y. Sahouria	[1]
13	Andrei Shibkov	[2] [4]
14	Marek Syrzycki	[2]