Rajeev Balasubramonian

	2009
22		Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter: Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches. HPCA 2009: 250-261
21		Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell: Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. HPCA 2009: 262-274
	2008
20		Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian: Scalable and reliable communication for hardware transactional memory. PACT 2008: 144-154
19		Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi: Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro 28(1): 69-79 (2008)
	2007
18		Naveen Muralimanohar, Rajeev Balasubramonian: Interconnect design considerations for large NUCA caches. ISCA 2007: 369-380
17		Niti Madan, Rajeev Balasubramonian: Leveraging 3D Technology for Improved Reliability. MICRO 2007: 223-235
16		Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi: Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. MICRO 2007: 3-14
15		Niti Madan, Rajeev Balasubramonian: Power Efficient Approaches to Redundant Multithreading. IEEE Trans. Parallel Distrib. Syst. 18(8): 1066-1079 (2007)
	2006
14		Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter: Interconnect-Aware Coherence Protocols for Chip Multiprocessors. ISCA 2006: 339-351
13		Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian: Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. ISPASS 2006: 100-111
12		Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter: Leveraging Wire Properties at the Microarchitecture Level. IEEE Micro 26(6): 40-52 (2006)
	2005
11		Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy: Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. HPCA 2005: 28-39
	2004
10		Rajeev Balasubramonian: Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures. ICS 2004: 326-335
	2003
9		Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi: Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. ISCA 2003: 275-286
8		Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu: Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. PACS 2003: 180-195
7		David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster: Dynamically Tuning Processor Resources with Adaptive Processing. IEEE Computer 36(12): 49-58 (2003)
6		Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas: A Dynamically Tunable Memory Hierarchy. IEEE Trans. Computers 52(10): 1243-1258 (2003)
	2002
5		Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott: Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. HPCA 2002: 29-42
4		Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott: Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. IEEE PACT 2002: 141-
	2001
3		Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi: Dynamically allocating processor resources between nearby and distant ILP. ISCA 2001: 26-37
2		Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi: Reducing the complexity of the register file in dynamic superscalar processors. MICRO 2001: 237-248
	2000
1		Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas: Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. MICRO 2000: 245-257

Coauthor Index

1	David H. Albonesi	[1] [2] [3] [4] [5] [6] [7] [9]
2	Manu Awasthi	[20] [22]
3	Pradip Bose	[7]
4	Alper Buyuktosunoglu	[1] [4] [6] [7] [8]
5	John B. Carter	[12] [14] [22]
6	Liqun Cheng	[12] [14]
7	Peter W. Cook	[7]
8	Steven G. Dropsho (Steve Dropsho)	[4] [7]
9	Sandhya Dwarkadas	[1] [2] [3] [4] [5] [6] [7] [8] [9]
10	Eby G. Friedman	[7]
11	Michael C. Huang	[7]
12	Ravishankar Iyer	[21]
13	Norman P. Jouppi	[16] [19]
14	Volkan Kursun	[7]
15	Niti Madan	[15] [17] [20] [21]
16	Grigorios Magklis	[4] [5] [7]
17	Srihari Makineni	[21]
18	Naveen Muralimanohar	[11] [12] [13] [14] [16] [18] [19] [20] [21]
19	Donald Newell	[21]
20	Seth H. Pugsley	[20]
21	Karthik Ramani	[11] [12] [13] [14]
22	Stanley Schuster	[7]
23	Michael L. Scott	[4] [5] [7]
24	Greg Semeraro	[4] [5] [7]
25	Viji Srinivasan	[8]
26	Kshitij Sudan	[22]
27	Aniruddha Udipi	[21]
28	Venkatanand Venkatachalapathy	[11]
29	Li Zhao	[21]

Colors in the list of coauthors