Kaustav Banerjee

	2009
47		Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee: High-speed low-power FinFET based domino logic. ASP-DAC 2009: 829-834
46		Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger: CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122
45		Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli: Graphene based transistors: physics, status and future perspectives. ISPD 2009: 65-66
44		Kaustav Banerjee: Graphene based nanomaterials for VLSI interconnect and energy-storage applications. SLIP 2009: 105-106
	2008
43		Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee: Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. DAC 2008: 250-255
42		Navin Srivastava, Roberto Suaya, Kaustav Banerjee: High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. DATE 2008: 426-431
41		Hamed F. Dadgour, Vivek De, Kaustav Banerjee: Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. ICCAD 2008: 270-277
40		Sheng-Chih Lin, Kaustav Banerjee: A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies. IEEE Trans. VLSI Syst. 16(11): 1488-1498 (2008)
	2007
39		Hamed F. Dadgour, Kaustav Banerjee: Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications. DAC 2007: 306-311
38		Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha: Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. VLSI Design 2007: 8
37		Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood: 3D Integration for Introspection. IEEE Micro 27(1): 77-83 (2007)
	2006
36		Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava: Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. ASP-DAC 2006: 223-230
35		Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood: Introspective 3D chips. ASPLOS 2006: 264-273
34		Kaustav Banerjee, Navin Srivastava: Are carbon nanotubes the future of VLSI interconnections? DAC 2006: 809-814
33		Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee: A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. DAC 2006: 977-982
32		Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee: A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. DAC 2006: 991-996
31		Sheng-Chih Lin, Kaustav Banerjee: An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. ICCAD 2006: 568-574
30		Rajiv V. Joshi, Kaustav Banerjee, André DeHon: Tutorial 1: Emerging Technologies for VLSI Design. ISQED 2006: 4
	2005
29		Navin Srivastava, Kaustav Banerjee: Performance analysis of carbon nanotube interconnects for VLSI applications. ICCAD 2005: 383-390
28		Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee: A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. ICCD 2005: 411-416
27		Vineet Wason, Kaustav Banerjee: A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. ISLPED 2005: 131-136
26		Navin Srivastava, Xiaoning Qi, Kaustav Banerjee: Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. ISQED 2005: 346-351
25		Lech Józwiak, Kaustav Banerjee: Plenary Session 2P. ISQED 2005: 461
24		Amir H. Ajami, Kaustav Banerjee, Massoud Pedram: Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 849-861 (2005)
23		Man Lung Mui, Kaustav Banerjee, Amit Mehrotra: Supply and power optimization in leakage-dominant technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1362-1371 (2005)
	2004
22		Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee: Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. DAC 2004: 884-887
21		Songqing Zhang, Vineet Wason, Kaustav Banerjee: A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. ISLPED 2004: 156-161
20		Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee: A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array. ISQED 2004: 259-264
19		Man Lung Mui, Kaustav Banerjee, Amit Mehrotra: Power Supply Optimization in sub-130 nm Leakage Dominant Technologies . ISQED 2004: 409-414
18		Adil Koukab, Kaustav Banerjee, Michel J. Declercq: Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 823-836 (2004)
	2003
17		Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu: A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits. ICCAD 2003: 497-503
	2002
16		Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier: Few electron devices: towards hybrid CMOS-SET integrated circuits. DAC 2002: 88-93
15		Adil Koukab, Kaustav Banerjee, Michel J. Declercq: Analysis and optimization of substrate noise coupling in single-chip RF transceiver design. ICCAD 2002: 309-316
14		Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq: A SET quantizer circuit aiming at digital communication system. ISCAS (5) 2002: 860-863
13		Kaustav Banerjee, Amit Mehrotra: Inductance Aware Interconnect Scaling. ISQED 2002: 43-47
12		Adrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, P. Renaud, C. Hibert, Philippe Flückiger, G. A. Racine: Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture. ISQED 2002: 496-501
11		Kaustav Banerjee, Amit Mehrotra: Analysis of on-chip inductance effects for distributed RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 904-915 (2002)
	2001
10		Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken: Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs. DAC 2001: 567-572
9		Kaustav Banerjee, Amit Mehrotra: Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects. DAC 2001: 798-803
8		Kaustav Banerjee, Amit Mehrotra: Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. ICCAD 2001: 158-164
7		TingYen Chiang, Kaustav Banerjee, Krishna Saraswat: Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. ICCAD 2001: 165-
6		Amir H. Ajami, Kaustav Banerjee, Massoud Pedram: Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion. ICCAD 2001: 44-48
5		Kaustav Banerjee, Massoud Pedram, Amir H. Ajami: Analysis and optimization of thermal issues in high-performance VLSI. ISPD 2001: 230-237
4		Choshu Ito, Kaustav Banerjee, Robert W. Dutton: Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. ISQED 2001: 117-122
	2000
3		Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna Saraswat: Multiple Si layer ICs: motivation, performance analysis, and design implications. DAC 2000: 213-220
2		Krishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur: Performance analysis and technology of 3-D ICs. SLIP 2000: 85-90
	1999
1		Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu: On Thermal Effects in Deep Sub-Micron VLSI Interconnects. DAC 1999: 885-891

Coauthor Index

1	Banit Agrawal	[32] [35] [37]
2	Amir H. Ajami	[5] [6] [10] [24]
3	Anirban Basu	[20] [22]
4	Luca Benini	[38]
5	Deming Chen	[46]
6	Mojy C. Chian	[46]
7	TingYen Chiang	[7]
8	Hamed F. Dadgour	[33] [39] [41]
9	Vivek De	[41]
10	André DeHon	[30] [46]
11	Michel J. Declercq	[12] [14] [15] [16] [18]
12	Nikil D. Dutt (Nikil Dutt)	[38]
13	Robert W. Dutton	[4]
14	Mohamed N. El-Zeftawi	[43]
15	Philippe Flückiger	[12]
16	R. Fritschi	[12]
17	Shinobu Fujita	[46]
18	Jacques Gautier	[16]
19	Lukas P. P. P. van Ginneken	[10]
20	C. Hibert	[12]
21	Chenming Hu	[1]
22	James Hutchby	[46]
23	Adrian M. Ionescu	[12] [14] [16] [17] [20]
24	Choshu Ito	[4]
25	Rajiv V. Joshi	[30] [33]
26	Lech Józwiak	[25]
27	Pawan Kapur	[2]
28	Yasin Khatami	[45]
29	Hanpei Koike	[47]
30	Adil Koukab	[15] [18]
31	Chaitanya Kshirsagar	[43] [45]
32	Kanishka Lahiri	[38]
33	Sheng-Chih Lin	[20] [22] [28] [31] [32] [35] [36] [37] [40]
34	Gian Luca Loi	[32]
35	Santanu Mahapatra	[14] [16] [17]
36	Amit Mehrotra	[1] [3] [8] [9] [11] [13] [19] [22] [23]
37	Man Lung Mui	[19] [23]
38	Shashidhar Mysore	[35] [37]
39	Sudeep Pasricha	[38]
40	Massoud Pedram	[5] [6] [10] [24]
41	Florent Pegeon	[17]
42	V. Pott	[12]
43	Xiaoning Qi	[26]
44	G. A. Racine	[12]
45	Seid Hadi Rasouli	[45] [47]
46	P. Renaud	[12]
47	Alberto L. Sangiovanni-Vincentelli	[1]
48	Krishna Saraswat	[2] [3] [7]
49	Timothy Sherwood	[32] [35] [37]
50	Shukri J. Souri	[2] [3]
51	Navin Srivastava	[26] [28] [29] [32] [34] [35] [36] [37] [42]
52	Roberto Suaya	[42]
53	Russell Tessier	[46]
54	Steve Trimberger	[46]
55	Vineet Wason	[21] [22] [27]
56	Christoph Wasshuber	[20]
57	Songqing Zhang	[21]

Colors in the list of coauthors