 | 2008 |
|---|
| 8 |       | Subhasis Banerjee,
G. Surendra,
S. K. Nandy:
On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation.
Journal of Systems Architecture - Embedded Systems Design 54(8): 797-815 (2008) |
| 2007 |
|---|
| 7 | | Subhasis Banerjee,
G. Surendra,
S. K. Nandy:
Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency.
ASP-DAC 2007: 884-889 |
| 2006 |
|---|
| 6 | | G. Surendra,
Subhasis Banerjee,
S. K. Nandy:
Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations.
J. Embedded Computing 2(1): 15-34 (2006) |
| 2004 |
|---|
| 5 | | G. Surendra,
Subhasis Banerjee,
S. K. Nandy:
Power-performance trade-off using pipeline delays.
ASP-DAC 2004: 384-386 |
| 4 | | Subhasis Banerjee,
G. Surendra,
S. K. Nandy:
Exploiting program execution phases to trade power and performance for media workload.
ASP-DAC 2004: 387-389 |
| 3 | | G. Surendra,
Subhasis Banerjee,
S. K. Nandy:
On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort.
WMPI 2004: 88-95 |
| 2003 |
|---|
| 2 | | G. Surendra,
Subhasis Banerjee,
S. K. Nandy:
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation.
DATE 2003: 10784-10789 |
| 1 | | G. Surendra,
Subhasis Banerjee,
S. K. Nandy:
On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications.
International Journal of Parallel Programming 31(6): 469-487 (2003) |
