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12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMing Xu, Gary Gréwal, Shawki Areibi, Charlie Obimbo, Dilip K. Banerji: Near-linear wirelength estimation for FPGA placement. CCECE 2009: 1198-1203
2006
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShouvik Chowdhury, Gary William Grewal, Dilip K. Banerji: Clustering Hanan Points to Reduce Vlsi Interconnect Routing Times. CCECE 2006: 1223-1227
2004
10no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPeng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji: A Fast Hierarchical Approach to FPGA Placement. ESA/VLSI 2004: 497-503
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji: Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees. VLSI Design 2004: 855-862
2003
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLZhibin Dai, Dilip K. Banerji: Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy. VLSI Design 2003: 85-90
1999
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWei Li, Dilip K. Banerji: Routability Prediction for Hierarchical FPGAs. Great Lakes Symposium on VLSI 1999: 256-259
1996
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJ. Shu, Thomas Charles Wilson, Dilip K. Banerji: Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. VLSI Design 1996: 73-76
1994
5no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLThomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji: An ILP-based approach to code generation. Code Generation for Embedded Processors 1994: 103-118
4no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLThomas Charles Wilson, Gary William Grewal, Dilip K. Banerji: An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. ICCD 1994: 581-586
1993
3no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLThomas Charles Wilson, Nilanjan Mukherjee, M. K. Garg, Dilip K. Banerji: An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. VLSI Design 1993: 192-197
1988
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLM. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia: Allocation of multiport memories in data path synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 7(4): 536-540 (1988)
1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLM. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders: A Semantic Approach for Modular Synthesis of VLSI Systems. Inf. Process. Lett. 27(1): 1-7 (1988)

Coauthor Index

1Shawki Areibi [10] [12]
2M. Balakrishnan [1] [2]
3Shouvik Chowdhury [11]
4Zhibin Dai [8]
5Peng Du [10]
6M. K. Garg [3]
7Gary William Grewal (Gary Gréwal) [4] [5] [9] [10] [11] [12]
8Shawn Henshall [5]
9Wei Li [7]
10James G. Linders [1] [2]
11Jayanti C. Majithia [2]
12Arun K. Majumdar [1] [2]
13Nilanjan Mukherjee [3]
14Charlie Obimbo [12]
15J. Shu [6]
16S. Sutarwala [1]
17Thomas Charles Wilson [3] [4] [5] [6] [9]
18Ming Xu [9] [12]

Colors in the list of coauthors

Copyright © Sat Nov 28 20:06:51 2009 by Michael Ley (ley@uni-trier.de)