Aditya Bansal

	2008
14		Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang: Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. ICCD 2008: 457-462
13		Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy: Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130
12		Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy: An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. JETC 4(3): (2008)
	2007
11		Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy: High Performance and Low Power Electronics on Flexible Substrate. DAC 2007: 274-275
10		Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy: Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2059-2068 (2007)
	2006
9		Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy: Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. ASP-DAC 2006: 237-242
8		Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy: A high density, carbon nanotube capacitor for decoupling applications. DAC 2006: 935-938
7		Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy: Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. DATE 2006: 983-988
6		Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy: Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. ICCAD 2006: 583-586
5		Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452
4		Aditya Bansal, Bipul Chandra Paul, Kaushik Roy: An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2765-2774 (2006)
	2005
3		Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224
2		Aditya Bansal, Kaushik Roy: Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. ISCAS (1) 2005: 1-4
	2004
1		Hari Ananthan, Aditya Bansal, Kaushik Roy: FinFET SRAM - Device and Circuit Design Considerations. ISQED 2004: 511-516

Coauthor Index

1	Hari Ananthan	[1] [3] [5]
2	Mark M. Budnik	[8]
3	Tamer Cakici	[3] [5]
4	Qikai Chen	[7]
5	Jung Hwan Choi	[6] [9] [10]
6	Ching-Te Chuang	[13] [14]
7	Swaroop Ghosh	[12]
8	Geng Han	[14]
9	Fook-Luen Heng	[14]
10	Kunhyuk Kang	[11]
11	Jae-Joon Kim	[13]
12	Keunwoo Kim	[13]
13	Jing Li	[11] [12]
14	Hamid Mahmoodi (Hamid Mahmoodi-Meimand)	[3] [5]
15	Mesut Meterelliyoz	[6] [9] [10]
16	Saibal Mukhopadhyay	[3] [5] [7] [13] [14]
17	Jayathi Murthy	[6] [9] [10]
18	Bipul Chandra Paul (Bipul C. Paul)	[4]
19	Arijit Raychowdhury	[8]
20	Kaushik Roy	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
21	Rama N. Singh	[14]
22	Siddharth Singh	[9]