 | 2008 |
|---|
| 21 |       | Tim Good,
Mohammed Benaissa:
Price to Provide RFID Security and Privacy?.
SECRYPT 2008: 209-213 |
| 20 | | Mohamed N. Hassan,
Mohammed Benaissa:
Low Area Scalable Montgomery Inversion Over GF(2m).
SECRYPT 2008: 363-367 |
| 19 |  | Tim Good,
Mohammed Benaissa:
ASIC Hardware Performance.
The eSTREAM Finalists 2008: 267-293 |
| 18 | | William N. Chelton,
Mohammed Benaissa:
Fast Elliptic Curve Cryptography on FPGA.
IEEE Trans. VLSI Syst. 16(2): 198-205 (2008) |
| 2007 |
|---|
| 17 | | Riyaz A. Patel,
Mohammed Benaissa,
Said Boussakta:
Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero.
IEEE Trans. Computers 56(11): 1484-1492 (2007) |
| 16 | | Riyaz A. Patel,
Mohammed Benaissa,
Said Boussakta:
Fast Modulo 2n - (2n-2+1) Addition: A New Class of Adder for RNS.
IEEE Trans. Computers 56(4): 572-576 (2007) |
| 2006 |
|---|
| 15 | | Tim Good,
Mohammed Benaissa:
AES as stream cipher on a small FPGA.
ISCAS 2006 |
| 14 | | William N. Chelton,
Mohammed Benaissa:
High-Speed Pipelined EGG Processor on FPGA.
SiPS 2006: 136-141 |
| 13 | | William N. Chelton,
Mohammed Benaissa:
Limiting Flexibility in Multiplication over GF(2m): A Design Methodology.
SiPS 2006: 153-156 |
| 12 | | Mohammed Benaissa,
Wei Ming Lim:
Design of flexible GF(2m) elliptic curve cryptography processors.
IEEE Trans. VLSI Syst. 14(6): 659-662 (2006) |
| 2005 |
|---|
| 11 | | Tim Good,
Mohammed Benaissa:
AES on FPGA from the Fastest to the Smallest.
CHES 2005: 427-440 |
| 2003 |
|---|
| 10 | | Yiqun Zhu,
Mohammed Benaissa:
Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique.
ASAP 2003: 360-368 |
| 9 | | Wei Ming Lim,
Mohammed Benaissa:
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and cryptography.
CODES+ISSS 2003: 53-58 |
| 8 | | Yiqun Zhu,
Mohammed Benaissa:
A novel ACS scheme for area-efficient Viterbi decoders.
ISCAS (2) 2003: 264-267 |
| 1998 |
|---|
| 7 | | Sebastian T. J. Fenn,
Michael Gössel,
Mohammed Benaissa,
David Taylor:
On-Line Error Detection for Bit-Serial Multipliers in GF(2m).
J. Electronic Testing 13(1): 29-40 (1998) |
| 1997 |
|---|
| 6 | | M. G. Parker,
Mohammed Benaissa:
Modular Arithmetic Using Low Order Redundant Bases.
IEEE Trans. Computers 46(5): 611-616 (1997) |
| 1996 |
|---|
| 5 | | Sebastian T. J. Fenn,
Mohammed Benaissa,
David Taylor:
GF(2^m) Multiplication and Division Over the Dual Basis.
IEEE Trans. Computers 45(3): 319-327 (1996) |
| 4 | | Sebastian T. J. Fenn,
Mohammed Benaissa,
David Taylor:
Finite field inversion over the dual basis.
IEEE Trans. VLSI Syst. 4(1): 134-137 (1996) |
| 1995 |
|---|
| 3 | | Sebastian T. J. Fenn,
Mohammed Benaissa,
David Taylor:
Bit-Serial Dual Basis Systolic Multipliers for GF 2m.
ISCAS 1995: 2000-2003 |
| 1994 |
|---|
| 2 | | Sebastian T. J. Fenn,
David Taylor,
Mohammed Benaissa:
A Dual Basis Systolic Divider for GF(2m).
ISCAS 1994: 307-310 |
| 1 | | M. G. Parker,
Mohammed Benaissa:
Fault-Tolerant Linear Convolution using Residue Number Systems.
ISCAS 1994: 441-444 |
