Subhrajit Bhattacharya Coauthor index DBLP Vis pubzone.org

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DBLP keys2005
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRuchir Puri, Leon Stok, Subhrajit Bhattacharya: Keeping hot chips cool. DAC 2005: 285-288
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin: A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. ISQED 2005: 482-487
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMartin Ohmacht, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Alan Gara, Mark Giampapa, Balaji Gopalsamy, Ruud A. Haring, Dirk Hoenicke, David J. Krolak, James A. Marcella, Ben J. Nathanson, Valentina Salapura, Michael E. Wazlowski: Blue Gene/L compute chip: Memory and Ethernet subsystem. IBM Journal of Research and Development 49(2-3): 255-264 (2005)
2003
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLReinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal: SEAS: a system for early analysis of SoCs. CODES+ISSS 2003: 150-155
2002
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJohn A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin: Early analysis tools for system-on-a-chip design. IBM Journal of Research and Development 46(6): 691-708 (2002)
2001
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLReinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau: Automating the Design of SOCs Using Cores. IEEE Design & Test of Computers 18(5): 32-45 (2001)
1999
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya: Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. ICCD 1999: 458-466
1998
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama: Verification of RTL generated from scheduled behavior in a high-level synthesis flow. ICCAD 1998: 517-524
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhrajit Bhattacharya, Sujit Dey, Franc Brglez: Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. ACM Trans. Design Autom. Electr. Syst. 3(2): 285-307 (1998)
1997
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta: An RTL methodology to enable low overhead combinational testing. ED&TC 1997: 146-152
7no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLToshiharu Asaka, Masaaki Yoshida, Subhrajit Bhattacharya, Sujit Dey: H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs. ITC 1997: 265-274
1996
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhrajit Bhattacharya, Sujit Dey: H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. VTS 1996: 74-80
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhrajit Bhattacharya, Sujit Dey, Franc Brglez: Fast true delay estimation during high level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1088-1105 (1996)
1994
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhrajit Bhattacharya, Sujit Dey, Franc Brglez: Clock Period Optimization During Resource Sharing and Assignment. DAC 1994: 195-200
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhrajit Bhattacharya, Sujit Dey, Franc Brglez: Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. DAC 1994: 491-496
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhrajit Bhattacharya, Sujit Dey, Franc Brglez: Provably correct high-level timing analysis without path sensitization. ICCAD 1994: 736-742
1993
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhrajit Bhattacharya, Franc Brglez, Sujit Dey: Transformations and resynthesis for testability of RT-level control-data path specifications. IEEE Trans. VLSI Syst. 1(3): 304-318 (1993)

Coauthor Index

1Toshiharu Asaka [7]
2Pranav Ashar [10] [11]
3Reinaldo A. Bergamaschi [12] [13] [14] [15]
4Daniel Brand [13]
5Franc Brglez [1] [2] [3] [4] [5] [9]
6John A. Darringer [13] [14] [16]
7Jean-Marc Daveau [12]
8Sujit Dey [1] [2] [3] [4] [5] [6] [7] [8] [9]
9Nagu R. Dhanwada [14]
10William E. Dougherty [14]
11Colleen Fellenz [12]
12Alan Gara [15]
13Mark Giampapa [15]
14Balaji Gopalsamy [15]
15Aarti Gupta [11]
16Ruud A. Haring [15]
17Andreas Herkersdorf [13]
18Dirk Hoenicke [15]
19David J. Krolak [15]
20William R. Lee [12]
21James A. Marcella [15]
22Joseph K. Morrell [13]
23Michael Muhlada [12]
24Akira Mukaiyama [10]
25Indira Nair [13] [14]
26Ben J. Nathanson [15]
27Martin Ohmacht [15]
28Daniel L. Ostapko [16]
29Sarala Paliwal [14]
30Ruchir Puri [17]
31Anand Raghunathan [10] [11]
32Patricia Sagmeister [13]
33Valentina Salapura [15]
34Bhaskar Sengupta [8]
35Youngsoo Shin [13] [14] [16]
36Leon Stok [17]
37Ronoldo Wagner [12]
38Michael E. Wazlowski [15]
39Foster White [12]
40Masaaki Yoshida [7]

Colors in the list of coauthors

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