 | 2009 |
|---|
| 85 |       | William Plishker,
Nimish Sane,
Shuvra S. Bhattacharyya:
Mode grouping for more effective generalized scheduling of dynamic dataflow applications.
DAC 2009: 923-926 |
| 84 | | William Plishker,
Nimish Sane,
Shuvra S. Bhattacharyya:
A generalized scheduling approach for dynamic dataflow applications.
DATE 2009: 111-116 |
| 83 | | Dongwon Lee,
Shuvra S. Bhattacharyya,
Wayne Wolf:
High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP Systems.
IEEE International Workshop on Rapid System Prototyping 2009: 137-144 |
| 82 | | Yen-Kuang Chen,
Lurng-Kuo Liu,
Shuvra S. Bhattacharyya:
Guest Editorial: Special Issue on Multi-Core Enabled Multimedia Applications & Architectures.
Signal Processing Systems 57(2): 121-122 (2009) |
| 2008 |
|---|
| 81 | | Chia-Jui Hsu,
José Luis Pino,
Shuvra S. Bhattacharyya:
Multithreaded simulation for synchronous dataflow graphs.
DAC 2008: 331-336 |
| 80 | | Sankalita Saha,
Jason Schlessman,
Sebastian Puthenpurayil,
Shuvra S. Bhattacharyya,
Wayne Wolf:
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications.
DATE 2008: 1220-1225 |
| 79 | | Joachim Falk,
Joachim Keinert,
Christian Haubelt,
Jürgen Teich,
Shuvra S. Bhattacharyya:
A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications.
EMSOFT 2008: 189-198 |
| 78 | | Omkar Dandekar,
William Plishker,
Shuvra S. Bhattacharyya,
Raj Shekhar:
Multiobjective Optimization of FPGA-Based Medical Image Registration.
FCCM 2008: 183-192 |
| 77 | | Hojin Kee,
Newton Petersen,
Jacob Kornerup,
Shuvra S. Bhattacharyya:
Systematic generation of FPGA-based FFT implementations.
ICASSP 2008: 1413-1416 |
| 76 | | Sankalita Saha,
Neal K. Bambha,
Shuvra S. Bhattacharyya:
Parameterized design framework for hardware implementation of particle filters.
ICASSP 2008: 1449-1452 |
| 75 | | William Plishker,
Nimish Sane,
Mary Kiemb,
Kapil Anand,
Shuvra S. Bhattacharyya:
Functional DIF for Rapid Prototyping.
IEEE International Workshop on Rapid System Prototyping 2008: 17-23 |
| 74 | | Chung-Ching Shen,
William Plishker,
Shuvra S. Bhattacharyya:
Design and optimization of a distributed, embedded speech recognition system.
IPDPS 2008: 1-8 |
| 73 | | William Plishker,
Nimish Sane,
Mary Kiemb,
Shuvra S. Bhattacharyya:
Heterogeneous Design in Functional DIF.
SAMOS 2008: 157-166 |
| 72 | | Ming-Yung Ko,
Chung-Ching Shen,
Shuvra S. Bhattacharyya:
Memory-constrained Block Processing for DSP Software Optimization.
Signal Processing Systems 50(2): 163-177 (2008) |
| 71 | | Shuvra S. Bhattacharyya,
Jarmo Takala,
Georgi Gaydadjiev:
Introduction to the Special Issue on Embedded Computing Systems for DSP.
Signal Processing Systems 50(2): 97-98 (2008) |
| 2007 |
|---|
| 70 | | Chung-Ching Shen,
Roni Kupershtok,
Shuvra S. Bhattacharyya,
Neil Goldsman:
Design Techniques for Streamlined Integration and Fault Tolerance in a Distributed Sensor System for Line-crossing Recognition.
ICCCN 2007: 1339-1344 |
| 69 | | Chung-Ching Shen,
Roni Kupershtok,
Bo Yang,
Felice Maria Vanin,
Xi Shao,
Datta Sheth,
Neil Goldsman,
Quirino Balzano,
Shuvra S. Bhattacharyya:
Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition.
ISCAS 2007: 2506-2509 |
| 68 | | Chung-Ching Shen,
William Plishker,
Shuvra S. Bhattacharyya,
Neil Goldsman:
An Energy-Driven Design Methodology for Distributing DSP Applications across Wireless Sensor Networks.
RTSS 2007: 214-226 |
| 67 | | Jani Boutellier,
Shuvra S. Bhattacharyya,
Olli Silvén:
Low-Overhead Run-Time Scheduling for Fine-Grained Acceleration of Signal Processing Systems.
SiPS 2007: 457-462 |
| 66 | | Perttu Salmela,
Chung-Ching Shen,
Shuvra S. Bhattacharyya,
Jarmo Takala:
Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations.
SiPS 2007: 475-480 |
| 65 | | Chia-Jui Hsu,
Ming-Yung Ko,
Shuvra S. Bhattacharyya,
Suren Ramasubbu,
José Luis Pino:
Efficient simulation of critical synchronous dataflow graphs.
ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
| 64 | | Ming-Yung Ko,
Praveen K. Murthy,
Shuvra S. Bhattacharyya:
Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls.
ACM Trans. Embedded Comput. Syst. 6(2): (2007) |
| 63 | | Shaoxiong Hua,
Gang Qu,
Shuvra S. Bhattacharyya:
Probabilistic design of multimedia embedded systems.
ACM Trans. Embedded Comput. Syst. 6(3): (2007) |
| 62 | | Ming-Yung Ko,
Claudiu Zissulescu,
Sebastian Puthenpurayil,
Shuvra S. Bhattacharyya,
Bart Kienhuis,
Ed F. Deprettere:
Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation.
IEEE Transactions on Signal Processing 55(6-2): 3126-3138 (2007) |
| 2006 |
|---|
| 61 | | Ed F. Deprettere,
Todor Stefanov,
Shuvra S. Bhattacharyya,
Mainak Sen:
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts.
ASAP 2006: 186-190 |
| 60 | | Dong-Ik Ko,
Shuvra S. Bhattacharyya:
The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications.
CODES+ISSS 2006: 52-57 |
| 59 | | Chia-Jui Hsu,
Suren Ramasubbu,
Ming-Yung Ko,
José Luis Pino,
Shuvra S. Bhattacharyya:
Efficient simulation of critical synchronous dataflow graphs.
DAC 2006: 893-898 |
| 58 | | Sankalita Saha,
Shuvra S. Bhattacharyya,
Wayne Wolf:
A Communication Interface for Multiprocessor Signal Processing Systems.
ESTImedia 2006: 127-132 |
| 57 | | Sankalita Saha,
Chung-Ching Shen,
Chia-Jui Hsu,
Gaurav Aggarwal,
Ashok Veeraraghavan,
Alan Sussman,
Shuvra S. Bhattacharyya:
Model-Based OpenMP Implementation of a 3D Facial Pose Tracking System.
ICPP Workshops 2006: 66-73 |
| 56 | | Ming-Yung Ko,
Chung-Ching Shen,
Shuvra S. Bhattacharyya:
Memory-constrained Block Processing Optimization for Synthesis of DSP Software.
ICSAMOS 2006: 137-143 |
| 55 | | Dong-Ik Ko,
Chung-Ching Shen,
Shuvra S. Bhattacharyya,
Neil Goldsman:
Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks.
SAMOS 2006: 142-154 |
| 54 | | Ivan Corretjer,
Chia-Jui Hsu,
Shuvra S. Bhattacharyya:
Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange Format.
SiPS 2006: 10-15 |
| 53 | | Shaoxiong Hua,
Gang Qu,
Shuvra S. Bhattacharyya:
Energy-efficient embedded software implementation on multiprocessor system-on-chip with multiple voltages.
ACM Trans. Embedded Comput. Syst. 5(2): 321-341 (2006) |
| 52 | | Vida Kianzad,
Shuvra S. Bhattacharyya:
Efficient Techniques for Clustering and Scheduling onto Embedded Multiprocessors.
IEEE Trans. Parallel Distrib. Syst. 17(7): 667-680 (2006) |
| 51 | | Mukul Khandelia,
Neal K. Bambha,
Shuvra S. Bhattacharyya:
Contention-conscious transaction ordering in multiprocessor DSP systems.
IEEE Transactions on Signal Processing 54(2): 556-569 (2006) |
| 50 | | Jürgen Teich,
Shuvra S. Bhattacharyya:
Analysis of Dataflow Programs with Interval-limited Data-rates.
VLSI Signal Processing 43(2-3): 247-258 (2006) |
| 2005 |
|---|
| 49 | | Vida Kianzad,
Shuvra S. Bhattacharyya,
Gang Qu:
CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems.
ASAP 2005: 191-197 |
| 48 | | Vida Kianzad,
Sankalita Saha,
Jason Schlessman,
Gaurav Aggarwal,
Shuvra S. Bhattacharyya,
Wayne Wolf,
Rama Chellappa:
An architectural level design methodology for embedded face detection.
CODES+ISSS 2005: 136-141 |
| 47 | | Neal K. Bambha,
Shuvra S. Bhattacharyya:
Communication strategies for shared-bus embedded multiprocessors.
EMSOFT 2005: 21-24 |
| 46 | | Jason Schlessman,
Sankalita Saha,
Wayne Wolf,
Shuvra S. Bhattacharyya:
An Extended Motion-Estimation Architecture Applied to Shape Recognition.
ICME 2005: 1504-1507 |
| 45 | | Chia-Jui Hsu,
Shuvra S. Bhattacharyya:
Porting DSP Applications across Design Tools Using the Dataflow Interchange Format.
IEEE International Workshop on Rapid System Prototyping 2005: 40-46 |
| 44 | | Chia-Jui Hsu,
Shuvra S. Bhattacharyya:
Software Synthesis from the Dataflow Interchange Format.
SCOPES 2005: 37-49 |
| 43 | | Sean Leventhal,
Lin Yuan,
Neal K. Bambha,
Shuvra S. Bhattacharyya,
Gang Qu:
DSP Address Optimization Using Evolutionary Algorithms.
SCOPES 2005: 91-98 |
| 42 | | Neal K. Bambha,
Shuvra S. Bhattacharyya:
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors.
IEEE Trans. Parallel Distrib. Syst. 16(2): 99-112 (2005) |
| 41 | | Michael J. Schulte,
Shuvra S. Bhattacharyya,
Robert Schreiber:
Guest Editorial.
VLSI Signal Processing 40(1): 5-6 (2005) |
| 40 | | Dong-Ik Ko,
Shuvra S. Bhattacharyya:
Modeling of Block-Based DSP Systems.
VLSI Signal Processing 40(3): 289-299 (2005) |
| 2004 |
|---|
| 39 | | Vida Kianzad,
Shuvra S. Bhattacharyya:
CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems.
ASAP 2004: 28-40 |
| 38 | | Ankush Varma,
Shuvra S. Bhattacharyya:
Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems.
DATE 2004: 161-167 |
| 37 | | Neal K. Bambha,
Shuvra S. Bhattacharyya,
Jürgen Teich,
Eckart Zitzler:
Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms.
GECCO (2) 2004: 383-384 |
| 36 | | Chia-Jui Hsu,
Fuat Keceli,
Ming-Yung Ko,
Shahrooz Shahparnia,
Shuvra S. Bhattacharyya:
DIF: An Interchange Format for Dataflow-Based Design Tools.
SAMOS 2004: 423-432 |
| 35 | | Jürgen Teich,
Shuvra S. Bhattacharyya:
Analysis of Dataflow Programs with Interval-Limited Data-Rates.
SAMOS 2004: 507-518 |
| 34 | | Ming-Yung Ko,
Praveen K. Murthy,
Shuvra S. Bhattacharyya:
Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition.
SCOPES 2004: 47-61 |
| 33 | | Praveen K. Murthy,
Shuvra S. Bhattacharyya:
Buffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications.
ACM Trans. Design Autom. Electr. Syst. 9(2): 212-237 (2004) |
| 32 |  | Neal K. Bambha,
Shuvra S. Bhattacharyya,
Jürgen Teich,
Eckart Zitzler:
Systematic integration of parameterized local search into evolutionary algorithms.
IEEE Trans. Evolutionary Computation 8(2): 137-155 (2004) |
| 31 | | Shuvra S. Bhattacharyya,
Praveen K. Murthy:
The CBP Parameter: A Module Characterization Approach for DSP Software Optimization.
VLSI Signal Processing 38(2): 131-146 (2004) |
| 2003 |
|---|
| 30 | | Shaoxiong Hua,
Gang Qu,
Shuvra S. Bhattacharyya:
Energy reduction techniques for multimedia applications with tolerance to deadline misses.
DAC 2003: 131-136 |
| 29 | | Shaoxiong Hua,
Gang Qu,
Shuvra S. Bhattacharyya:
Energy-Efficient Multi-processor Implementation of Embedded Software.
EMSOFT 2003: 257-273 |
| 28 | | Shaoxiong Hua,
Gang Qu,
Shuvra S. Bhattacharyya:
Exploring the Probabilistic Design Space of Multimedia Systems.
IEEE International Workshop on Rapid System Prototyping 2003: 233- |
| 27 | | Neal K. Bambha,
Shuvra S. Bhattacharyya,
Gary Euliss:
Design Considerations for Optically Connected Systems on Chip.
IWSOC 2003: 299-303 |
| 26 | | Ming-Yung Ko,
Shuvra S. Bhattacharyya:
Partitioning for DSP Software Synthesis.
SCOPES 2003: 344-358 |
| 25 | | Bruce L. Jacob,
Shuvra S. Bhattacharyya:
Introduction to the two special issues on memory.
ACM Trans. Embedded Comput. Syst. 2(1): 1-4 (2003) |
| 24 | | Jörg Henkel,
Xiaobo Hu,
Shuvra S. Bhattacharyya:
Guest Editors' Introduction: Taking on the Embedded System Design Challenge.
IEEE Computer 36(4): 35-37 (2003) |
| 2002 |
|---|
| 23 | | Shuvra S. Bhattacharyya,
Trevor N. Mudge,
Wayne Wolf,
Ahmed Amine Jerraya:
Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002
ACM 2002 |
| 22 | | Gary Spivey,
Shuvra S. Bhattacharyya,
Kazuo Nakajima:
A Component Architecture for FPGA-Based, DSP System Design.
ASAP 2002: 41- |
| 21 | | Bishnupriya Bhattacharya,
Shuvra S. Bhattacharyya:
Consistency Analysis of Reconfigurable Dataflow Specifications.
Embedded Processor Design Challenges 2002: 1-17 |
| 20 | | Bruce L. Jacob,
Shuvra S. Bhattacharyya:
Introduction to the two special issues on memory.
ACM Trans. Embedded Comput. Syst. 1(1): 2-5 (2002) |
| 2001 |
|---|
| 19 | | Neal K. Bambha,
Shuvra S. Bhattacharyya,
Jürgen Teich,
Eckart Zitzler:
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors.
CODES 2001: 243-248 |
| 18 | | Vida Kianzad,
Shuvra S. Bhattacharyya:
Multiprocessor Clustering for Embedded Systems.
Euro-Par 2001: 697-701 |
| 17 | | Praveen K. Murthy,
Shuvra S. Bhattacharyya:
Shared buffer implementations of signal processing systems usinglifetime analysis techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 177-198 (2001) |
| 2000 |
|---|
| 16 | | Mukul Khandelia,
Shuvra S. Bhattacharyya:
Contention-Conscious Transaction Ordering in Embedded Multiprocessors.
ASAP 2000: 276- |
| 15 | | Praveen K. Murthy,
Shuvra S. Bhattacharyya:
Shared Memory Implementations of Synchronous Dataflow Specifications.
DATE 2000: 404-410 |
| 14 | | Bishnupriya Bhattacharya,
Shuvra S. Bhattacharyya:
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems.
IEEE International Workshop on Rapid System Prototyping 2000: 84-89 |
| 13 | | Neal K. Bambha,
Shuvra S. Bhattacharyya:
A Joint Power/Performance Optimization Algorithm for Multiprocessor Systems using a Period Graph Construct.
ISSS 2000: 91-99 |
| 12 | | Eckart Zitzler,
Jürgen Teich,
Shuvra S. Bhattacharyya:
Multidimensional Exploration of Software Implementations for DSP Algorithms.
VLSI Signal Processing 24(1): 83-98 (2000) |
| 1999 |
|---|
| 11 | | Jürgen Teich,
Eckart Zitzler,
Shuvra S. Bhattacharyya:
3D exploration of software schedules for DSP algorithms.
CODES 1999: 168-172 |
| 10 | | Praveen K. Murthy,
Shuvra S. Bhattacharyya:
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications.
ISSS 1999: 78-84 |
| 9 | | Shuvra S. Bhattacharyya,
Praveen K. Murthy,
Edward A. Lee:
Synthesis of Embedded Software from Synchronous Dataflow Specifications.
VLSI Signal Processing 21(2): 151-166 (1999) |
| 1998 |
|---|
| 8 | | Jürgen Teich,
Eckart Zitzler,
Shuvra S. Bhattacharyya:
Buffer Memory Optimization in DSP Applications - An Evolutionary Approach.
PPSN 1998: 885-896 |
| 1997 |
|---|
| 7 | | Shuvra S. Bhattacharyya,
Praveen K. Murthy,
Edward A. Lee:
Optimized software synthesis for synchronous dataflow.
ASAP 1997: 250-262 |
| 6 | | Praveen K. Murthy,
Shuvra S. Bhattacharyya,
Edward A. Lee:
Joint Minimization of Code and Data for Synchronous Dataflow Programs.
Formal Methods in System Design 11(1): 41-70 (1997) |
| 1996 |
|---|
| 5 | | Shuvra S. Bhattacharyya,
Sundararajan Sriram,
Edward A. Lee:
Latency-constrained Resynchronization for Multiprocessor DSP Implementation.
ASAP 1996: 365-380 |
| 4 | | Shuvra S. Bhattacharyya,
Sundararajan Sriram,
Edward A. Lee:
Self-Timed Resynchronization: A Post-Optimization for Static Multiprocessor Schedules.
IPPS 1996: 199-205 |
| 1995 |
|---|
| 3 | | Shuvra S. Bhattacharyya,
Sundararajan Sriram,
Edward A. Lee:
Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems.
ASAP 1995: 298-309 |
| 1994 |
|---|
| 2 | | Shuvra S. Bhattacharyya,
Edward A. Lee:
Looped Schedules for Dataflow Descriptions of Multirate Signal Processing Algorithms.
Formal Methods in System Design 5(3): 183-205 (1994) |
| 1993 |
|---|
| 1 | | Shuvra S. Bhattacharyya,
Edward A. Lee:
Scheduling synchronous dataflow graphs for efficient looping.
VLSI Signal Processing 6(3): 271-288 (1993) |
