 | 2009 |
| 12 |  | Muthu Manikandan Baskaran,
Nagavijayalakshmi Vydyanathan,
Uday Bondhugula,
J. Ramanujam,
Atanas Rountev,
P. Sadayappan:
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors.
PPOPP 2009: 219-228 |
| 11 |  | Lakshminarayanan Renganarayana,
Uday Bondhugula,
Salem Derisavi,
Alexandre E. Eichenberger,
Kevin O'Brien:
Compact multi-dimensional kernel extraction for register tiling.
SC 2009 |
| 2008 |
| 10 |  | Uday Bondhugula,
Muthu Manikandan Baskaran,
Sriram Krishnamoorthy,
J. Ramanujam,
Atanas Rountev,
P. Sadayappan:
Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model.
CC 2008: 132-146 |
| 9 |  | Muthu Manikandan Baskaran,
Uday Bondhugula,
Sriram Krishnamoorthy,
J. Ramanujam,
Atanas Rountev,
P. Sadayappan:
A compiler framework for optimization of affine loop nests for gpgpus.
ICS 2008: 225-234 |
| 8 |  | Uday Bondhugula,
Muthu Manikandan Baskaran,
Albert Hartono,
Sriram Krishnamoorthy,
J. Ramanujam,
Atanas Rountev,
P. Sadayappan:
Towards effective automatic parallelization for multicore systems.
IPDPS 2008: 1-5 |
| 7 |  | Uday Bondhugula,
Albert Hartono,
J. Ramanujam,
P. Sadayappan:
A practical automatic polyhedral parallelizer and locality optimizer.
PLDI 2008: 101-113 |
| 6 |  | Muthu Manikandan Baskaran,
Uday Bondhugula,
Sriram Krishnamoorthy,
J. Ramanujam,
Atanas Rountev,
P. Sadayappan:
Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories.
PPOPP 2008: 1-10 |
| 2007 |
| 5 |  | Sriram Krishnamoorthy,
Muthu Manikandan Baskaran,
Uday Bondhugula,
J. Ramanujam,
Atanas Rountev,
P. Sadayappan:
Effective automatic parallelization of stencil computations.
PLDI 2007: 235-244 |
| 4 |  | Uday Bondhugula,
J. Ramanujam,
P. Sadayappan:
Automatic mapping of nested loops to FPGAS.
PPOPP 2007: 101-111 |
| 2006 |
| 3 |  | Uday Bondhugula,
Ananth Devulapalli,
James Dinan,
Joseph Fernando,
Pete Wyckoff,
Eric Stahlberg,
P. Sadayappan:
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths.
FCCM 2006: 152-164 |
| 2 |  | Uday Bondhugula,
Ananth Devulapalli,
Joseph Fernando,
Pete Wyckoff,
P. Sadayappan:
Parallel FPGA-based all-pairs shortest-paths in a directed graph.
IPDPS 2006 |
| 2005 |
| 1 |  | Sayantan Sur,
Uday Bondhugula,
Amith R. Mamidala,
Hyun-Wook Jin,
Dhabaleswar K. Panda:
High Performance RDMA Based All-to-All Broadcast for InfiniBand Clusters.
HiPC 2005: 148-157 |