Soumitra Bose

	2007
17		Soumitra Bose, Vishwani D. Agrawal: Delay Test Quality Evaluation Using Bounded Gate Delays. VTS 2007: 23-28
	2006
16		Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram: Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. VTS 2006: 88-93
	2005
15		Soumitra Bose, Amit Nandi: Schematic array models for associative and non-associative memory circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1582-1593 (2005)
	2004
14		Soumitra Bose, Amit Nandi: Extraction of Schematic Array Models for Memory Circuits. DATE 2004: 570-577
13		Soumitra Bose: Modeling Custom Digital Circuits for Test. J. Electronic Testing 20(6): 591-609 (2004)
	2002
12		Soumitra Bose: Automated Modeling of Custom Digital Circuits for Test. DATE 2002: 954-963
	1998
11		Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Deriving Logic Systems for Path Delay Test Generation. IEEE Trans. Computers 47(8): 829-846 (1998)
	1997
10		Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski: Algorithms for Switch Level Delay Fault Simulation. ITC 1997: 982-991
	1995
9		Soumitra Bose, Vishwani D. Agrawal: Sequential logic path delay test generation by symbolic analysis. Asian Test Symposium 1995: 353-
	1993
8		Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Generation of Compact Delay Tests by Multiple-Path Activation. ITC 1993: 714-723
7		Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: A Path Delay Fault Simulator for Sequential Circuits. VLSI Design 1993: 269-274
6		Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Path delay fault simulation of sequential circuits. IEEE Trans. VLSI Syst. 1(4): 453-461 (1993)
5		Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: The optimistic update theorem for path delay testing in sequential circuits. J. Electronic Testing 4(3): 285-290 (1993)
	1992
4		Soumitra Bose, Prathima Agrawal: Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers. DAC 1992: 332-335
3		Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov: PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. J. Autom. Reasoning 8(2): 153-181 (1992)
	1989
2		Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov: PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses LICS 1989: 80-89
	1988
1		P. E. Allen, Soumitra Bose, Edmund M. Clarke, Spiro Michaylov: PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. CADE 1988: 764-765

Coauthor Index

1	Prathima Agrawal	[4] [5] [6] [7] [8] [11]
2	Vishwani D. Agrawal	[5] [6] [7] [8] [9] [10] [11] [16] [17]
3	P. E. Allen	[1]
4	Edmund M. Clarke	[1] [2] [3]
5	Vijay Gangaram	[16]
6	David E. Long	[2] [3]
7	Spiro Michaylov	[1] [2] [3]
8	Amit Nandi	[14] [15]
9	Thomas G. Szymanski	[10]

Colors in the list of coauthors