 | 2009 |
|---|
| 10 |       | Krzysztof Kepa,
Fearghal Morgan,
Krzysztof Kosciuszkiewicz,
Lars Braun,
Michael Hübner,
Jürgen Becker:
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.
ARC 2009: 62-73 |
| 2008 |
|---|
| 9 | | Oliver Sander,
Lars Braun,
Michael Hübner,
Jürgen Becker:
Data reallocation by exploiting FPGA configuration mechanisms.
ARC 2008: 308-313 |
| 8 | | Josef Angermeier,
Mateusz Majer,
Jürgen Teich,
Lars Braun,
T. Schwalb,
Philipp Graf,
Michael Hübner,
Jürgen Becker,
Enno Lübbers,
Marco Platzner,
Christopher Claus,
Walter Stechele,
Andreas Herkersdorf,
Markus Rullmann,
Renate Merker:
Fine grain reconfigurable architectures.
FPL 2008: 348 |
| 7 | | Christopher Claus,
Bin Zhang,
Walter Stechele,
Lars Braun,
Michael Hübner,
Jürgen Becker:
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput.
FPL 2008: 535-538 |
| 6 | | Lars Braun,
Katarina Paulsson,
Herrmann Krömer,
Michael Hübner,
Jürgen Becker:
Data path driven waveform-like reconfiguration.
FPL 2008: 607-610 |
| 5 | | Michael Hübner,
Lars Braun,
Diana Göhringer,
Jürgen Becker:
Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems.
IPDPS 2008: 1-6 |
| 4 | | Alexander Klimm,
Lars Braun,
Jürgen Becker:
An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores.
IPDPS 2008: 1-7 |
| 2007 |
|---|
| 3 | | Lars Braun,
Michael Hübner,
Jürgen Becker,
Thomas Perschke,
Volker Schatz,
Stefan Bach:
Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.
FPL 2007: 688-691 |
| 2 | | Michael Hübner,
Lars Braun,
Jürgen Becker,
Christopher Claus,
Walter Stechele:
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs.
ISVLSI 2007: 41-46 |
| 2004 |
|---|
| 1 | | Michael Hübner,
Michael Ullmann,
Lars Braun,
A. Klausmann,
Jürgen Becker:
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.
FPL 2004: 1037-1041 |
