| 2009 | ||
|---|---|---|
| 5 | André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler: Increasing the accuracy of SAT-based debugging. DATE 2009: 1326-1331 | |
| 2007 | ||
| 4 | Cécile Braunstein, Emmanuelle Encrenaz: Using CTL formulae as component abstraction in a design and verification flow. ACSD 2007: 80-89 | |
| 3 | Cécile Braunstein, Emmanuelle Encrenaz: CTL-property Transformations along an Incremental Design Process. STTT 9(1): 77-88 (2007) | |
| 2006 | ||
| 2 | Cécile Braunstein, Emmanuelle Encrenaz: Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter. IEEE International Workshop on Rapid System Prototyping 2006: 103-109 | |
| 2005 | ||
| 1 | Cécile Braunstein, Emmanuelle Encrenaz: CTL-Property Transformations Along an Incremental Design Process. Electr. Notes Theor. Comput. Sci. 128(6): 263-278 (2005) | |
| 1 | Rolf Drechsler | [5] |
| 2 | Emmanuelle Encrenaz-Tiphène (Emmanuelle Encrenaz) | [1] [2] [3] [4] |
| 3 | Görschwin Fey | [5] |
| 4 | Ulrich Kühne | [5] |
| 5 | André Sülflow | [5] |