| 2009 | ||
|---|---|---|
| 31 | Amit Verma, Ajay K. Verma, Philip Brisk, Paolo Ienne: Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC 2009: 203-209 | |
| 30 | Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne: A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219 | |
| 29 | Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon: Way Stealing: cache-assisted automatic instruction set extensions. DAC 2009: 31-36 | |
| 28 | José Luis Ayala, David Atienza, Philip Brisk: Thermal-aware data flow analysis. DAC 2009: 613-614 | |
| 27 | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj: 3D configuration caching for 2D FPGAs. FPGA 2009: 286 | |
| 26 | Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne: MPSoC Design Using Application-Specific Architecturally Visible Communication. HiPEAC 2009: 183-197 | |
| 25 | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. TRETS 2(2): (2009) | |
| 2008 | ||
| 24 | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Efficient synthesis of compressor trees on FPGAs. ASP-DAC 2008: 138-143 | |
| 23 | Ajay K. Verma, Philip Brisk, Paolo Ienne: Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC 2008: 334-339 | |
| 22 | Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Design space exploration for field programmable compressor trees. CASES 2008: 207-216 | |
| 21 | Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon: Speculative DMA for architecturally visible storage in instruction set extensions. CODES+ISSS 2008: 243-248 | |
| 20 | Ajay K. Verma, Philip Brisk, Paolo Ienne: Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE 2008: 1250-1255 | |
| 19 | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE 2008: 1256-1261 | |
| 18 | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: A novel FPGA logic block for improved arithmetic performance. FPGA 2008: 171-180 | |
| 17 | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 | |
| 16 | Jani Boutellier, Veeranjaneyulu Sadhanala, Christophe Lucarz, Philip Brisk, Marco Mattavelli: Scheduling of dataflow models within the Reconfigurable Video Coding framework. SiPS 2008: 182-187 | |
| 15 | Ajay K. Verma, Philip Brisk, Paolo Ienne: Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1761-1774 (2008) | |
| 2007 | ||
| 14 | Ajay K. Verma, Philip Brisk, Paolo Ienne: Rethinking custom ISE identification: a new processor-agnostic method. CASES 2007: 125-134 | |
| 13 | Philip Brisk, Ajay K. Verma, Paolo Ienne: An optimistic and conservative register assignment heuristic for chordal graphs. CASES 2007: 209-217 | |
| 12 | Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar: Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337 | |
| 11 | Ajay K. Verma, Philip Brisk, Paolo Ienne: Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC 2007: 404-409 | |
| 10 | Philip Brisk, Ajay K. Verma, Paolo Ienne: Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD 2007: 172-179 | |
| 9 | Philip Brisk, Majid Sarrafzadeh: Interference graphs for procedures in static single information form are interval graphs. SCOPES 2007: 101-110 | |
| 2006 | ||
| 8 | Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh: Layout driven data communication optimization for high level synthesis. DATE 2006: 1185-1190 | |
| 7 | Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh: Optimal register sharing for high-level synthesis of SSA form programs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 772-779 (2006) | |
| 2005 | ||
| 6 | Philip Brisk, Jamie Macbeth, Ani Nahapetian, Majid Sarrafzadeh: A dictionary construction technique for code compression systems with echo instructions. LCTES 2005: 105-114 | |
| 5 | Roozbeh Jafari, Foad Dabiri, Philip Brisk, Majid Sarrafzadeh: Adaptive and fault tolerant medical vest for life-critical medical monitoring. SAC 2005: 272-279 | |
| 2004 | ||
| 4 | Philip Brisk, Adam Kaplan, Majid Sarrafzadeh: Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. DAC 2004: 395-400 | |
| 3 | Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh: Instruction Selection for Compilers that Target Architectures with Echo Instructions. SCOPES 2004: 229-243 | |
| 2003 | ||
| 2 | Adam Kaplan, Philip Brisk, Ryan Kastner: Data communication estimation and reduction for reconfigurable systems. DAC 2003: 616-621 | |
| 2002 | ||
| 1 | Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh: Instruction generation and regularity extraction for reconfigurable processors. CASES 2002: 262-269 | |