| 2011 | ||
|---|---|---|
| 13 | Jeffrey L. Burns: Technology trends and implications on SoC design. SoCC 2011: 386 | |
| 2004 | ||
| 12 | Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown: Analysis and Optimization of Enhanced MTCMOS Scheme. VLSI Design 2004: 234-239 | |
| 2003 | ||
| 11 | Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown: A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. ICCAD 2003: 689-692 | |
| 10 | Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns: Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. ICCD 2003: 134-139 | |
| 9 | Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown: Efficient techniques for gate leakage estimation. ISLPED 2003: 100-103 | |
| 8 | Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman: A semi-custom voltage-island technique and its application to high-speed serial links. ISLPED 2003: 60-65 | |
| 7 | Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns: Leakage and leakage sensitivity computation for combinational circuits. ISLPED 2003: 96-99 | |
| 1999 | ||
| 6 | Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns: Performance Driven Synthesis for Pass-Transistor Logic. VLSI Design 1999: 372-377 | |
| 1998 | ||
| 5 | Jeffrey L. Burns, Jack A. Feldman: C5M-a control-logic layout synthesis system for high-performance microprocessors. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 14-23 (1998) | |
| 1997 | ||
| 4 | Jeffrey L. Burns, Jack A. Feldman: C5M - a control logic layout synthesis system for high-performance microprocessors. ISPD 1997: 110-115 | |
| 1994 | ||
| 3 | Venkat K. R. Chiluvuri, Israel Koren, Jeffrey L. Burns: The Effect of Wire Length Minimization on Yield. DFT 1994: 97-105 | |
| 1988 | ||
| 2 | Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma: Techniques for multilayer channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 698-712 (1988) | |
| 1986 | ||
| 1 | Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli: Chameleon: a new multi-layer channel router. DAC 1986: 495-502 | |
| 1 | Emrah Acar | [7] |
| 2 | Adnan Aziz | [6] |
| 3 | Douglas Braun | [1] [2] |
| 4 | Richard B. Brown | [9] [11] [12] |
| 5 | Juan Antonio Carballo | [8] |
| 6 | Gary D. Carpenter | [10] |
| 7 | Vikas Chandra | [10] |
| 8 | Venkat K. R. Chiluvuri | [3] |
| 9 | Srinivas Devadas | [1] [2] |
| 10 | Anirudh Devgan | [7] [9] |
| 11 | Jack A. Feldman | [4] [5] |
| 12 | Malay K. Ganai | [6] |
| 13 | Israel Koren | [3] |
| 14 | Frank Liu | [11] |
| 15 | Tai-Hung Liu | [6] |
| 16 | Ying Liu | [7] |
| 17 | Hi-Keung Tony Ma | [1] [2] |
| 18 | Kartikeya Mayaram | [1] [2] |
| 19 | Sani R. Nassif | [7] |
| 20 | V. Robert Norman | [8] |
| 21 | Rahul M. Rao | [7] [9] [11] [12] |
| 22 | Fabio Romeo | [1] [2] |
| 23 | Alberto L. Sangiovanni-Vincentelli | [1] [2] |
| 24 | Haihua Su | [7] |
| 25 | Ivan Vo | [8] |
| 26 | Seung-Moon Yoo | [8] |
Colors in the list of coauthors
Last update Fri May 25 01:42:58 2012 CET by the DBLP Team —
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