| 2007 | ||
|---|---|---|
| 34 | Mohammad Tehranipoor, Kenneth M. Butler: Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs. IEEE Design & Test of Computers 24(3): 214-215 (2007) | |
| 33 | Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler: Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 896-906 (2007) | |
| 2006 | ||
| 32 | Kenneth M. Butler: Guest Editor's Introduction: ITC Helps Get More Out of Test. IEEE Design & Test of Computers 23(5): 388-389 (2006) | |
| 2004 | ||
| 31 | Kenneth M. Butler: Sure You Can Get to 100 DPPM in Deep Submicron, But It'll Cost Ya. ITC 2004: 1419 | |
| 30 | Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington: Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques. ITC 2004: 355-364 | |
| 2003 | ||
| 29 | Jayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger: A Case Study of IR-Drop in Structured At-Speed Testing. ITC 2003: 1098-1104 | |
| 28 | Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang: Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs. IEEE Design & Test of Computers 20(5): 6-7 (2003) | |
| 2002 | ||
| 27 | Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech: Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges . ITC 2002: 1120-1129 | |
| 26 | Kenneth M. Butler: Is ITC Bored with Board Test? ITC 2002: 1237 | |
| 25 | Hari Balachandran, Kenneth M. Butler, Neil Simpson: Facilitating Rapid First Silicon Debug. ITC 2002: 628-637 | |
| 2001 | ||
| 24 | Frank F. Hsu, Kenneth M. Butler, Janak H. Patel: A case study on the implementation of the Illinois Scan Architecture. ITC 2001: 538-547 | |
| 23 | Jayashree Saxena, Kenneth M. Butler, Lee Whetsel: An analysis of power reduction techniques in scan testing. ITC 2001: 670-677 | |
| 22 | Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang: Defect-Oriented Testing and Defective-Part-Level Prediction. IEEE Design & Test of Computers 18(1): 31-41 (2001) | |
| 2000 | ||
| 21 | Jayashree Saxena, Kenneth M. Butler: An empirical study on the effects of test type ordering on overall test efficiency. ITC 2000: 408-416 | |
| 20 | Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler: Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. ITC 2000: 729-738 | |
| 1999 | ||
| 19 | Hari Balachandran, Jason Parker, Gordon Gammie, John W. Olson, Craig Force, Kenneth M. Butler, Sri Jandhyala: Expediting ramp-to-volume production. ITC 1999: 103-112 | |
| 18 | Hari Balachandran, Jason Parker, Daniel Shupp, Stephanie Butler, Kenneth M. Butler, Craig Force, Jason Smith: Correlation of logical failures to a suspect process step. ITC 1999: 458-476 | |
| 17 | Kenneth M. Butler: A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data. ITC 1999: 839-847 | |
| 16 | Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer: REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. VTS 1999: 268-274 | |
| 15 | Kenneth M. Butler: Estimating the Economic Benefits of DFT. IEEE Design & Test of Computers 16(1): 71-79 (1999) | |
| 1998 | ||
| 14 | Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess: On applying non-classical defect models to automated diagnosis. ITC 1998: 748-757 | |
| 1997 | ||
| 13 | Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly: So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. ITC 1997: 1037-1038 | |
| 12 | Kenneth M. Butler: The stuck-at fault: it ain't over 'til it's over. ITC 1997: 1165 | |
| 11 | Kenneth M. Butler: Stuck-at fault: a fault model for the next millennium. ITC 1997: 1166 | |
| 10 | David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler: Bridging Fault Diagnosis in the Absence of Physical Information. ITC 1997: 887-893 | |
| 9 | Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken: An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing. VTS 1997: 459 | |
| 8 | Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Kinra, Jayashree Saxena: Automated Diagnosis in Testing and Failure Analysis. IEEE Design & Test of Computers 14(3): 83-89 (1997) | |
| 1996 | ||
| 7 | Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Jones, Jayashree Saxena: Integrating Automated Diagnosis into the Testing and Failure Analysis Operations. ITC 1996: 934 | |
| 1995 | ||
| 6 | Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell: Test Generation and Design for Test for a Large Multiprocessing DSP. ITC 1995: 149-156 | |
| 5 | Kenneth M. Butler: Deep Submicron: Is Test Up to the Challenge? ITC 1995: 923 | |
| 1991 | ||
| 4 | Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer: Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. DAC 1991: 417-420 | |
| 3 | Don E. Ross, Kenneth M. Butler, M. Ray Mercer: Exact ordered binary decision diagram size when representing classes of symmetric functions. J. Electronic Testing 2(3): 243-259 (1991) | |
| 1990 | ||
| 2 | Kenneth M. Butler, M. Ray Mercer: The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. DAC 1990: 673-678 | |
| 1988 | ||
| 1 | Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler: CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. DAC 1988: 597-600 | |