Ney Calazans
List of publications from the DBLP Bibliography Server - FAQ
| 2009 | ||
|---|---|---|
| 39 | Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans: Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. DATE 2009: 634-639 | |
| 2008 | ||
| 38 | Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans: Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI 2008: 347-352 | |
| 37 | Guilherme Guindani, Cezar Reinbrecht, Thiago Raupp, Ney Calazans, Fernando Gehm Moraes: NoC Power Estimation at the RTL Abstraction Level. ISVLSI 2008: 475-478 | |
| 36 | Fernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans: MOTIM: an industrial application using nocs. SBCCI 2008: 182-187 | |
| 35 | Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert: Evaluating the robustness of secure triple track logic through prototyping. SBCCI 2008: 193-198 | |
| 2007 | ||
| 34 | Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans: SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. ICCD 2007: 541-546 | |
| 33 | Luis Carlos Caruso, Guilherme Guindani, Hugo Schmitt, Ney Calazans, Fernando Moraes: SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems. IEEE International Workshop on Rapid System Prototyping 2007: 27-33 | |
| 32 | Ewerson Carvalho, Ney Calazans, Fernando Moraes: Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. IEEE International Workshop on Rapid System Prototyping 2007: 34-40 | |
| 31 | César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Evaluation of Algorithms for Low Energy Mapping onto NoCs. ISCAS 2007: 389-392 | |
| 30 | Erico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes: MOTIM - A Scalable Architecture for Ethernet Switches. ISVLSI 2007: 451-452 | |
| 29 | Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. ISVLSI 2007: 459-460 | |
| 28 | Leandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes: A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. ReCoSoC 2007: 23-30 | |
| 27 | Everton Carara, Fernando Moraes, Ney Calazans: Router architecture for high-performance NoCs. SBCCI 2007: 111-116 | |
| 26 | Leonel Tedesco, Fernando Moraes, Ney Calazans: Buffer sizing for QoS flows in wormhole packet switching NoCs. SBCCI 2007: 99-104 | |
| 25 | Aline Mello, Ney Laert Vilar Calazans: Rate-based scheduling policy for QoS flows in networks on chip. VLSI-SoC 2007: 140-145 | |
| 24 | César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel: Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique CoRR abs/0710.4738: (2007) | |
| 23 | Aline Mello, Leandro Möller, Ney Calazans, Fernando Moraes: MultiNoC: A Multiprocessing System Enabled by a Network on Chip CoRR abs/0710.4843: (2007) | |
| 2006 | ||
| 22 | Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes: Reconfigurable Systems Enabled by a Network-on-Chip. FPL 2006: 1-4 | |
| 21 | Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes: Infrastructure for dynamic reconfigurable systems: choices and trade-offs. SBCCI 2006: 44-49 | |
| 20 | Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes: Application driven traffic modeling for NoCs. SBCCI 2006: 62-67 | |
| 2005 | ||
| 19 | Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans: MAIA: a framework for networks on chip generation and verification. ASP-DAC 2005: 49-52 | |
| 18 | César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel: Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. DATE 2005: 502-507 | |
| 17 | César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans: Models for Embedded Application Mapping onto NoCs: Timing Analysis. IEEE International Workshop on Rapid System Prototyping 2005: 17-23 | |
| 16 | Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans: Energy and latency evaluation of NoC topologies. ISCAS (6) 2005: 5866-5869 | |
| 15 | Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes: Virtual channels in networks on chip: implementation and evaluation on hermes NoC. SBCCI 2005: 178-183 | |
| 14 | Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes: Traffic generation and performance evaluation for mesh-based NoCs. SBCCI 2005: 184-189 | |
| 13 | José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin: Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. SBCCI 2005: 196-201 | |
| 12 | César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis: Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. VLSI-SoC 2005: 179-194 | |
| 2004 | ||
| 11 | Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes: MultiNoC: A Multiprocessing System Enabled by a Network on Chip. DATE 2004: 234-239 | |
| 10 | Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes: MultiNoC: A Multiprocessing System Enabled by a Network on Chip. DATE 2004: 234-239 | |
| 9 | Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato: FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. FPL 2004: 1042-1046 | |
| 8 | Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes: PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems. SBCCI 2004: 10-15 | |
| 7 | Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost: HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integration 38(1): 69-93 (2004) | |
| 2003 | ||
| 6 | Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans: Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. DATE 2003: 11122-11123 | |
| 5 | Daniel Mesquita, Fernando Gehm Moraes, José Palma, Leandro Möller, Ney Laert Vilar Calazans: Remote and Partial Reconfiguration of FPGAs: Tools and Trends. IPDPS 2003: 177 | |
| 4 | Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara: From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. SBCCI 2003: 355- | |
| 3 | Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans: A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. VLSI-SOC 2003: 318-323 | |
| 2001 | ||
| 2 | Ney Laert Vilar Calazans, Fernando Gehm Moraes, Delfim Luiz Torok, Andrey V. Andreoli: Projeto para Prototipação de um IP Soft Core MAC Ethernet. RITA 8(1): 23-41 (2001) | |
| 1994 | ||
| 1 | Ney Laert Vilar Calazans: Boolean constrained encoding: a new formulation and a case study. ICCAD 1994: 702-706 | |