 | 2009 |
|---|
| 9 |       | Andrea Calimera,
Enrico Macii,
Massimo Poncino:
NBTI-aware sleep transistor design for reliable power-gating.
ACM Great Lakes Symposium on VLSI 2009: 333-338 |
| 8 | | Leticia Maria Veiras Bolzani,
Andrea Calimera,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Enabling concurrent clock and power gating in an industrial design flow.
DATE 2009: 334-339 |
| 2008 |
|---|
| 7 | | Andrea Calimera,
Enrico Macii,
Massimo Poncino,
R. Iris Bahar:
Temperature-insensitive synthesis using multi-vt libraries.
ACM Great Lakes Symposium on VLSI 2008: 5-10 |
| 6 | | Andrea Calimera,
Luca Benini,
Enrico Macii:
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints.
DATE 2008: 973-978 |
| 5 | | Enrico Macii,
Leticia Maria Veiras Bolzani,
Andrea Calimera,
Alberto Macii,
Massimo Poncino:
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.
DSD 2008: 298-303 |
| 4 | | Ashoka Visweswara Sathanur,
Andrea Calimera,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.
ISCAS 2008: 2761-2764 |
| 3 | | Andrea Calimera,
R. Iris Bahar,
Enrico Macii,
Massimo Poncino:
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.
ISLPED 2008: 217-220 |
| 2007 |
|---|
| 2 | | Andrea Calimera,
Antonio Pullini,
Ashoka Visweswara Sathanur,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.
ACM Great Lakes Symposium on VLSI 2007: 501-504 |
| 1 | | Ashoka Visweswara Sathanur,
Andrea Calimera,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
DATE 2007: 1544-1549 |
