Ashutosh Chakraborty

	2009
13		Ashutosh Chakraborty, Anurag Kumar, David Z. Pan: RegPlace: a high quality open-source placement framework for structured ASICs. DAC 2009: 442-447
12		Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan: Analysis and optimization of NBTI induced clock skew in gated clock trees. DATE 2009: 296-299
11		Ashutosh Chakraborty, David Z. Pan: On stress aware active area sizing, gate sizing, and repeater insertion. ISPD 2009: 35-42
	2008
10		Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan: An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC 2008: 702-707
9		Ashutosh Chakraborty, Sean X. Shi, David Z. Pan: Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. DATE 2008: 849-855
8		Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. IEEE Trans. VLSI Syst. 16(6): 639-649 (2008)
7		Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino: Implementation of a thermal management unit for canceling temperature-dependent clock skew variations. Integration 41(1): 2-8 (2008)
	2006
6		Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino: Thermal resilient bounded-skew clock tree optimization methodology. DATE 2006: 832-837
5		Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino: Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. ISCAS 2006
4		Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Dynamic thermal clock skew compensation using tunable delay buffers. ISLPED 2006: 162-167
3		Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino: Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. PATMOS 2006: 214-224
	2005
2		Ashutosh Chakraborty, Enrico Macii, Massimo Poncino: Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. PATMOS 2005: 297-307
	2003
1		Pradeep Varma, Ashutosh Chakraborty: Low-Voltage, Double-Edge-Triggered Flip Flop. PATMOS 2003: 11-20

Coauthor Index

1	Luca Benini	[4] [8]
2	Tung-Chieh Chen	[10]
3	Karthik Duraisami	[3] [4] [5] [6] [7] [8]
4	Gokul Ganesan	[12]
5	Anurag Kumar	[13]
6	Alberto Macii	[3] [4] [5] [6] [7] [8]
7	Enrico Macii	[2] [3] [4] [5] [6] [7] [8]
8	David Z. Pan (David Zhigang Pan)	[9] [10] [11] [12] [13]
9	Massimo Poncino	[2] [3] [4] [5] [6] [7] [8]
10	Anand Rajaram	[12]
11	Ashoka Visweswara Sathanur	[3] [4] [5] [7] [8]
12	Sean X. Shi	[9]
13	Prassanna Sithambaram	[3] [4] [5] [6] [7] [8]
14	Pradeep Varma	[1]

Colors in the list of coauthors