| 2008 |
| 22 | EE | Bhargav S. Gulavani,
Supratik Chakraborty,
Aditya V. Nori,
Sriram K. Rajamani:
Automatically Refining Abstract Interpretations.
TACAS 2008: 443-458 |
| 21 | EE | Dina Thomas,
Supratik Chakraborty,
Paritosh K. Pandya:
Efficient guided symbolic reachability using reachability expressions.
STTT 10(2): 113-129 (2008) |
| 2006 |
| 20 | EE | Joycee Mekie,
Supratik Chakraborty,
Dinesh K. Sharma,
Girish Venkataramani,
P. S. Thiagarajan:
Interface Design for Rationally Clocked GALS Systems.
ASYNC 2006: 160-171 |
| 19 | EE | Dina Thomas,
Supratik Chakraborty,
Paritosh K. Pandya:
Efficient Guided Symbolic Reachability Using Reachability Expressions.
TACAS 2006: 120-134 |
| 18 | EE | Supratik Chakraborty,
Joycee Mekie,
Dinesh K. Sharma:
Reasoning about synchronization in GALS systems.
Formal Methods in System Design 28(2): 153-169 (2006) |
| 2005 |
| 17 | EE | Babita Sharma,
Paritosh K. Pandya,
Supratik Chakraborty:
Bounded Validity Checking of Interval Duration Logic.
TACAS 2005: 301-316 |
| 2004 |
| 16 | EE | Joycee Mekie,
Supratik Chakraborty,
Dinesh K. Sharma:
Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework.
VLSI Design 2004: 559-564 |
| 2002 |
| 15 | EE | Subir K. Roy,
S. Ramesh,
Supratik Chakraborty,
Tsuneo Nakata,
Sreeranga P. Rajan:
Functional Verification of System on Chips-Practices, Issues and Challenges.
ASP-DAC 2002: 11-13 |
| 14 | EE | Supratik Chakraborty,
Rajeev Murgai:
Layout-driven Timing Optimization by Generalized De Morgan Transform.
ASP-DAC 2002: 647-654 |
| 13 | EE | Rohan Angrish,
Supratik Chakraborty:
Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delay.
ASYNC 2002: 99-108 |
| 12 | EE | Subir K. Roy,
S. Ramesh,
Supratik Chakraborty,
Tsuneo Nakata,
Sreeranga P. Rajan:
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).
VLSI Design 2002: 11-13 |
| 11 | EE | Supratik Chakraborty,
Rajeev Murgai:
Layout-Driven Timing Optimization by Generalized De Morgan Transform.
VLSI Design 2002: 647-654 |
| 2001 |
| 10 | EE | Supratik Chakraborty,
Rajeev Murgai:
Complexity Of Minimum-Delay Gate Resizing.
VLSI Design 2001: 425-430 |
| 2000 |
| 9 | EE | Kenneth Y. Yun,
Kevin W. James,
R. H. Fairlie-Cuninghame,
Supratik Chakraborty,
Rene L. Cruz:
A self-timed real-time sorting network.
IEEE Trans. VLSI Syst. 8(3): 356-363 (2000) |
| 1999 |
| 8 | EE | Supratik Chakraborty,
Kenneth Y. Yun,
David L. Dill:
Timing analysis of asynchronous systems using time separation of events.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1061-1076 (1999) |
| 1997 |
| 7 | EE | Supratik Chakraborty,
David L. Dill,
Kun-Yung Chang,
Kenneth Y. Yun:
Timing Analysis of Extended Burst-Mode Circuits.
ASYNC 1997: 101-111 |
| 6 | EE | Supratik Chakraborty,
David L. Dill:
More Accurate Polynomial-Time Min-Max Timing Simulation.
ASYNC 1997: 112- |
| 5 | EE | Supratik Chakraborty,
David L. Dill:
Approximate algorithms for time separation of events.
ICCAD 1997: 190-194 |
| 1996 |
| 4 | | Supratik Chakraborty,
Dipanwita Roy Chowdhury,
Parimal Pal Chaudhuri:
Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines.
IEEE Trans. Computers 45(7): 769-781 (1996) |
| 1993 |
| 3 | EE | Dipanwita Roy Chowdhury,
Supratik Chakraborty,
B. Vamsi,
B. Pal Chaudhuri:
Cellular automata based synthesis of easily and fully testable FSMs.
ICCAD 1993: 650-653 |
| 2 | | Dipanwita Roy Chowdhury,
Supratik Chakraborty,
Parimal Pal Chaudhuri:
Synthesis of Self-Checking Sequential Machines Using Cellular Automata.
VLSI Design 1993: 107 |
| 1 | | S. Nandi,
Vamsi Boppana,
Supratik Chakraborty,
Parimal Pal Chaudhuri,
Samir Roy:
Delay Fault Test Generation with Cellular Automata.
VLSI Design 1993: 281-286 |