 | 2009 |
|---|
| 14 |       | Ying-Zu Lin,
Soon-Jyh Chang,
Yen-Ting Liu:
A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process.
IEICE Transactions 92-C(2): 258-268 (2009) |
| 2008 |
|---|
| 13 | | Hsin-Hung Ou,
Soon-Jyh Chang,
Bin-Da Liu:
Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture.
IEICE Transactions 91-A(2): 461-468 (2008) |
| 12 | | Chia-Ling Wei,
Lu-Yao Wu,
Hsiu-Hui Yang,
Chien-Hung Tsai,
Bin-Da Liu,
Soon-Jyh Chang:
A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter.
IEICE Transactions 91-C(5): 809-812 (2008) |
| 11 | | Hsin-Hung Ou,
Bin-Da Liu,
Soon-Jyh Chang:
A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture.
IEICE Transactions 91-C(9): 1480-1487 (2008) |
| 2007 |
|---|
| 10 | | Hsin-Wen Ting,
Cheng-Wu Lin,
Bin-Da Liu,
Soon-Jyh Chang:
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST.
J. Electronic Testing 23(6): 549-558 (2007) |
| 2006 |
|---|
| 9 | | Heng-Yao Lin,
Hui-Hsien Tsai,
Bin-Da Liu,
Jar-Ferr Yang,
Soon-Jyh Chang:
An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders.
APCCAS 2006: 255-258 |
| 8 | | Jin-Fu Lin,
Soon-Jyh Chang:
A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique.
ISCAS 2006 |
| 7 | | Yen-Ting Liu,
Lih-Yih Chiou,
Soon-Jyh Chang:
Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop.
ISCAS 2006 |
| 2004 |
|---|
| 6 | | Chih-Haur Huang,
Kuen-Jong Lee,
Soon-Jyh Chang:
A Low-Cost Diagnosis Methodology for Pipelined A/D Converters.
Asian Test Symposium 2004: 296-301 |
| 5 | | Hsin-Wen Ting,
Bin-Da Liu,
Soon-Jyh Chang:
A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters.
Asian Test Symposium 2004: 52-57 |
| 2003 |
|---|
| 4 | | Kuen-Jong Lee,
Soon-Jyh Chang,
Ruei-Shiuan Tzeng:
A Sigma-Delta Modulation Based BIST Scheme for A/D Converters.
Asian Test Symposium 2003: 124-129 |
| 3 | | Soon-Jyh Chang,
Chung-Len Lee,
Jwu E. Chen:
Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits.
J. Inf. Sci. Eng. 19(4): 637-651 (2003) |
| 2002 |
|---|
| 2 | | Soon-Jyh Chang,
Chung-Len Lee,
Jwu E. Chen:
Structural Fault Based Specification Reduction for Testing Analog Circuits.
J. Electronic Testing 18(6): 571-581 (2002) |
| 1997 |
|---|
| 1 | | Soon-Jyh Chang,
Chung-Len Lee,
Jwu E. Chen:
Functional test pattern generation for CMOS operational amplifier.
VTS 1997: 267-273 |
