Tsin-Yuan Chang

	2008
19		Hung-Chih Lin, Bou-Ching Fung, Tsin-Yuan Chang: A current mode adaptive on-time control scheme for fast transient DC-DC converters. ISCAS 2008: 2602-2605
18		Chung-Yi Li, Chih-Feng Chien, Jin-Hua Hong, Tsin-Yuan Chang: An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES. ISVLSI 2008: 503-506
	2006
17		Chung-Yi Li, Jiung-Sheng Chen, Tsin-Yuan Chang: A chaos-based pseudo random number generator using timing-based reseeding method. ISCAS 2006
	2005
16		Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang: On-chip accumulated jitter measurement for phase-locked loops. ASP-DAC 2005: 1184-1187
	2004
15		Kae-Jiun Mo, Shao-Sheng Yang, Tsin-Yuan Chang: Timing measurement unit with multi-stage TVC for embedded memories. ASP-DAC 2004: 565-566
14		Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang: A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier. Asian Test Symposium 2004: 272-276
13		Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang: A Built-In Parametric Timing Measurement Unit. IEEE Design & Test of Computers 21(4): 322-330 (2004)
	2003
12		Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong: A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers. ISCAS (5) 2003: 365-368
	2002
11		Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang: An Access Timing Measurement Unit of Embedded Memory. Asian Test Symposium 2002: 104-
10		Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang: An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters. Asian Test Symposium 2002: 266-
	2001
9		Jeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang: An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters. Asian Test Symposium 2001: 423-
8		Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A low-cost CMOS time interval measurement core. ISCAS (4) 2001: 190-193
7		Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A built-in timing parametric measurement unit. ITC 2001: 315-322
	2000
6		Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang: A realistic fault model for flash memories. Asian Test Symposium 2000: 274-281
5		Tsin-Yuan Chang, Yervant Zorian: SoC Testing and P1500 Standard. Asian Test Symposium 2000: 492-
	1999
4		Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang: A Programmable BIST Core for Embedded DRAM. IEEE Design & Test of Computers 16(1): 59-70 (1999)
	1990
3		Chin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang: Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement. DAC 1990: 327-332
2		Chin-Long Wey, Tsin-Yuan Chang: An efficient output phase assignment for PLA minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 9(1): 1-7 (1990)
	1988
1		Chin-Long Wey, Tsin-Yuan Chang: PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs. DAC 1988: 421-426

Coauthor Index

1	Jiung-Sheng Chen	[17]
2	Chih-Feng Chien	[18]
3	Jyhyeung Ding	[3]
4	Bou-Ching Fung	[19]
5	Pao-Lin Guo	[12]
6	Jin-Hua Hong	[12] [18]
7	Yea-Ling Horng	[6]
8	Ming-Jun Hsiao	[7] [8] [9] [10] [11] [13] [14]
9	Sheng-Hung Hsieh	[10]
10	Chih-Tsun Huang	[4]
11	Jing-Reng Huang	[4] [6] [7] [8] [13]
12	Shu-Rong Lee	[11]
13	Chih-Feng Li	[16]
14	Chung-Yi Li	[17] [18]
15	Hung-Chih Lin	[19]
16	Kae-Jiun Mo	[15]
17	Yi-Ming Sheng	[14]
18	Jeng-Horng Tsai	[9]
19	Chin-Long Wey	[1] [2] [3]
20	Cheng-Wen Wu	[4]
21	Chi-Feng Wu	[4]
22	Shao-Shen Yang	[7] [8]
23	Shao-Sheng Yang	[12] [15] [16]
24	Yervant Zorian	[5]

Colors in the list of coauthors