 | 2009 |
|---|
| 10 |       | Liang-Bi Chen,
Ruei-Ting Gu,
Wei-Sheng Huang,
Chien-Chou Wang,
Wen-Chi Shiue,
Tsung-Yu Ho,
Yun-Nan Chang,
Shen-Fu Hsiao,
Chung-Nan Lee,
Ing-Jer Huang:
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics.
ASP-DAC 2009: 131-132 |
| 9 |  | Yun-Nan Chang,
Ting-Chi Tong:
A Lossless Buffer Compression Scheme for 3D Graphic System.
CGVR 2009: 116-121 |
| 2008 |
|---|
| 8 | | Yun-Nan Chang,
Ting-Chi Tong:
An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization.
Signal Processing Systems 53(3): 435-448 (2008) |
| 2005 |
|---|
| 7 | | Yun-Nan Chang:
Design of an efficient memory-based DVB-T channel decoder.
ISCAS (5) 2005: 5019-5022 |
| 2003 |
|---|
| 6 | | Yun-Nan Chang:
Design of soft-output Viterbi decoders with hybrid trace-back processing.
ISCAS (2) 2003: 69-72 |
| 5 | | Yun-Nan Chang:
An Efficient In-Place VLSI Architecture for Viterbi Algorithm.
VLSI Signal Processing 33(3): 317-324 (2003) |
| 1998 |
|---|
| 4 | | Yun-Nan Chang,
Ching-Yi Wang,
Keshab K. Parhi:
Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units.
VLSI Signal Processing 19(3): 243-256 (1998) |
| 1997 |
|---|
| 3 | | Yun-Nan Chang,
Janardhan H. Satyanarayana,
Keshab K. Parhi:
Design and Implementation of Low-Power Digit-Serial Multipliers.
ICCD 1997: 186-195 |
| 1996 |
|---|
| 2 | | Yun-Nan Chang,
Ching-Yi Wang,
Keshab K. Parhi:
Loop-List Scheduling for Heterogeneous Functional Units.
Great Lakes Symposium on VLSI 1996: 2-7 |
| 1 | | Janardhan H. Satyanarayana,
Keshab K. Parhi,
Leilei Song,
Yun-Nan Chang:
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.
ICCD 1996: 492-499 |
