Karam S. Chatha

	2009
48		Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula: A scalable parallel H.264 decoder on the cell broadband engine architecture. CODES+ISSS 2009: 353-362
47		Glenn Leary, Karam S. Chatha: Automated technique for design of NoC with minimal communication latency. CODES+ISSS 2009: 471-480
46		Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha: Throughput optimal task allocation under thermal constraints for multi-core processors. DAC 2009: 776-781
45		Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha: Performance optimal speed control of multi-core processors under thermal constraints. DATE 2009: 1548-1551
44		Sushu Zhang, Karam S. Chatha, Goran Konjevod: Near optimal battery-aware energy management. ISLPED 2009: 249-254
	2008
43		Sushu Zhang, Karam S. Chatha: Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures. ASP-DAC 2008: 61-66
42		Michael A. Baker, Viswesh Parameswaran, Karam S. Chatha, Baoxin Li: Power reduction via macroblock prioritization for power aware H.264 video applications. CODES+ISSS 2008: 261-266
41		Sushu Zhang, Karam S. Chatha: System-level thermal aware design of applications with uncertain execution time. ICCAD 2008: 242-249
40		Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod: Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1425-1438 (2008)
	2007
39		Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod: Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. ASP-DAC 2007: 184-190
38		Christopher Ostler, Karam S. Chatha, Goran Konjevod: Approximation Algorithm for Process Mapping on Network Processor Architectures. ASP-DAC 2007: 577-582
37		Glenn Leary, Krishna Mehta, Karam S. Chatha: Performance and resource optimization of NoC router architecture for master and slave IP cores. CODES+ISSS 2007: 155-160
36		Michael A. Baker, Aviral Shrivastava, Karam S. Chatha: Smart driver for power reduction in next generation bistable electrophoretic display technology. CODES+ISSS 2007: 197-202
35		Christopher Ostler, Karam S. Chatha: Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures. DAC 2007: 801-804
34		Christopher Ostler, Karam S. Chatha: An ILP formulation for system-level application mapping on network processor architectures. DATE 2007: 99-104
33		Sushu Zhang, Karam S. Chatha: Approximation algorithm for the temperature-aware scheduling problem. ICCAD 2007: 281-288
32		Sushu Zhang, Karam S. Chatha, Goran Konjevod: Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules. ISLPED 2007: 225-230
31		Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan: ILP and heuristic techniques for system-level design on network processor architectures. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
30		Krishnan Srinivasan, Karam S. Chatha: Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints. Integration 40(3): 326-354 (2007)
29		Lina Peng, K. Selçuk Candan, Christopher B. Mayer, Karam S. Chatha, Kyung Dong Ryu: Optimization of media processing workflows with adaptive operator behaviors. Multimedia Tools Appl. 33(3): 245-272 (2007)
	2006
28		Lina Peng, Gisik Kwon, Yinpeng Chen, K. Selçuk Candan, Hari Sundaram, Karam S. Chatha, Maria Luisa Sapino: Modular Design of Media Retrieval Workflows Using ARIA. CIVR 2006: 491-494
27		Krishnan Srinivasan, Karam S. Chatha: Layout aware design of mesh based NoC architectures. CODES+ISSS 2006: 136-141
26		Krishnan Srinivasan, Karam S. Chatha: A low complexity heuristic for design of custom network-on-chip architectures. DATE 2006: 130-135
25		Krishnan Srinivasan, Karam S. Chatha: A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. ISQED 2006: 352-357
24		Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod: Linear-programming-based techniques for synthesis of network-on-chip architectures. IEEE Trans. VLSI Syst. 14(4): 407-420 (2006)
	2005
23		Lina Peng, Gisik Kwon, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram, Yinpeng Chen: Media processing workflow design and execution with ARIA. ACM Multimedia 2005: 800-801
22		Krishnan Srinivasan, Karam S. Chatha: SAGA: synthesis technique for guaranteed throughput NoC architectures. ASP-DAC 2005: 489-494
21		Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod: An automated technique for topology and route generation of application specific on-chip interconnection networks. ICCAD 2005: 231-237
20		Krishnan Srinivasan, Karam S. Chatha: A technique for low energy mapping and routing in network-on-chip architectures. ISLPED 2005: 387-392
19		Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha: System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures. ISVLSI 2005: 110-116
18		Nagendran Rangan, Karam S. Chatha: A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. VLSI Design 2005: 564-569
17		Krishnan Srinivasan, Karam S. Chatha: ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. VLSI Design 2005: 623-628
16		Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha: Quality-of-service and error control techniques for mesh-based network-on-chip architectures. Integration 38(3): 353-382 (2005)
	2004
15		Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha: Quality-of-service and error control techniques for network-on-chip architectures. ACM Great Lakes Symposium on VLSI 2004: 45-50
14		Lina Peng, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram: ARIA: an adaptive and programmable media-flow architecture for interactive arts. ACM Multimedia 2004: 532-535
13		Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha: A Power and Performance Model for Network-on-Chip Architectures. DATE 2004: 1250-1255
12		Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod: Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures. ICCD 2004: 422-429
11		Krishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha: A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder. ISVLSI 2004: 313-316
10		Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha: System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. ISVLSI 2004: 39-45
9		K. Selçuk Candan, Lina Peng, Kyung Dong Ryu, Karam S. Chatha, Christopher B. Mayer: Efficient Stream Routing in Quality- and Resource-Adaptive Flow Architectures. Multimedia Information Systems 2004: 30-39
8		Krishnan Srinivasan, Karam S. Chatha: An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. VLSI Design 2004: 255-260
	2002
7		Karam S. Chatha, Ranga Vemuri: Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Trans. VLSI Syst. 10(3): 193-208 (2002)
	2001
6		Karam S. Chatha, Ranga Vemuri: MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. CODES 2001: 42-47
	1999
5		Karam S. Chatha, Ranga Vemuri: Hardware-Software Codesign for Dynamically Reconfigurable Architectures. FPL 1999: 175-184
4		Karam S. Chatha, Ranga Vemuri: An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. IEEE International Workshop on Rapid System Prototyping 1999: 134-139
	1998
3		Karam S. Chatha, Ranga Vemuri: RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. CODES 1998: 139-143
2		Karam S. Chatha, Ranga Vemuri: A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. ISSS 1998: 145-151
1		Karam S. Chatha, Ranga Vemuri: Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. International Workshop on Rapid System Prototyping 1998: 218-224

Coauthor Index

1	Michael A. Baker	[36] [42] [48]
2	Nilanjan Banerjee	[13] [15] [16]
3	K. Selçuk Candan	[9] [14] [23] [28] [29]
4	Yinpeng Chen	[23] [28]
5	Pravin Dalale	[48]
6	Vinay Hanumaiah	[45] [46]
7	Goran Konjevod	[12] [21] [24] [32] [38] [39] [40] [44]
8	Gisik Kwon	[23] [28]
9	Glenn Leary	[37] [47]
10	Baoxin Li	[42]
11	Christopher B. Mayer	[9] [29]
12	Jason McCollum	[19]
13	Krishna Mehta	[37]
14	Christopher Ostler	[19] [31] [34] [35] [38]
15	Viswesh Parameswaran	[42]
16	Lina Peng	[9] [14] [23] [28] [29]
17	Vijay Ramamurthi	[10] [11] [31]
18	Vijaykumar Ramamurthi	[19]
19	Nagendran Rangan	[18]
20	Ravishankar Rao	[46]
21	Kyung Dong Ryu	[9] [14] [23] [29]
22	Maria Luisa Sapino	[28]
23	Aviral Shrivastava	[36]
24	Krishnan Srinivasan	[8] [10] [11] [12] [17] [20] [21] [22] [24] [25] [26] [27] [30] [31] [39] [40]
25	Hari Sundaram	[14] [23] [28]
26	Nagender Telkar	[10]
27	Praveen Vellanki	[13] [15] [16]
28	Ranga Vemuri	[1] [2] [3] [4] [5] [6] [7]
29	Sarma B. K. Vrudhula	[45] [46] [48]
30	Sushu Zhang	[32] [33] [41] [43] [44]

Colors in the list of coauthors