Santanu Chattopadhyay

	2009
39		Ajit Pal, Santanu Chattopadhyay: Synthesis & Testing for Low Power. VLSI Design 2009: 37-38
38		Saurabh Chaudhury, Krishna Teja Sistla, Santanu Chattopadhyay: Genetic algorithm-based FSM synthesis with area-power trade-offs. Integration 42(3): 376-384 (2009)
	2008
37		Santanu Kundu, Santanu Chattopadhyay: Mesh-of-tree deterministic routing for network-on-chip architecture. ACM Great Lakes Symposium on VLSI 2008: 343-346
36		Mayur Bubna, Naresh Shenoy, Santanu Chattopadhyay: An efficient greedy approach to PLA folding. ISCAS 2008: 1356-1359
35		Rafiahamed Shaik, Mrityunjoy Chakraborty, Santanu Chattopadhyay: An efficient finite precision realization of the block adaptive decision feedback equalizer. ISCAS 2008: 1910-1913
34		Tapas K. Maiti, Santanu Chattopadhyay: Don't care filling for power minimization in VLSI circuit testing. ISCAS 2008: 2637-2640
33		Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay: Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. ISVLSI 2008: 269-274
	2007
32		Chandan Giri, Dilip Kumar Reddy Tipparthi, Santanu Chattopadhyay: Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling. ICCTA 2007: 141-145
31		Chandan Giri, B. Mallikarjuna Rao, Santanu Chattopadhyay: Test Data Compression by Spilt-VIHC (SVIHC). ICCTA 2007: 146-150
30		Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay: Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach. ICIC (2) 2007: 1032-1041
29		Chandan Giri, Santanu Chattopadhyay: Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs. ISCAS 2007: 3679-3682
28		Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay: A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs. VLSI-SoC 2007: 320-323
	2006
27		Saurabh Chaudhury, Santanu Chattopadhyay, J. Srinivasa Rao: Synthesis of Finite State Machines for Low Power and Testability. APCCAS 2006: 1434-1437
	2005
26		Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay: Flip-flop chaining architecture for power-efficient scan during test application. Asian Test Symposium 2005: 410-413
25		Santanu Chattopadhyay, Manas Kumar Dewangan: A Combinational Logic Mapper for Actel's SX/AX Family. VLSI Design 2005: 669-672
24		Santanu Chattopadhyay: Area Conscious State Assignment with Flip-Flop and Output Polarity Selection for Finite State Machine Synthesis?A Genetic Algorithm Approach. Comput. J. 48(4): 443-450 (2005)
	2004
23		Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay: Model checking on state transition diagram. ASP-DAC 2004: 412-417
22		D. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar: Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs. VLSI Design 2004: 79-84
	2003
21		Santanu Chattopadhyay, K. Sudarsana Reddy: Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips. VLSI Design 2003: 341-346
20		Santanu Chattopadhyay, Naveen Choudhary: Genetic Algorithm based Approach for Low Power Combinational Circuit Testing. VLSI Design 2003: 552-
19		Rohit Pandey, Santanu Chattopadhyay: Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach". VLSI Design 2003: 79-84
	2002
18		Santanu Chattopadhyay: Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata. Asian Test Symposium 2002: 188-193
	2001
17		Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay: A Novel Strategy to Test Core Based Designs. VLSI Design 2001: 122-127
16		Prabir Dasgupta, Santanu Chattopadhyay, Parimal Pal Chaudhuri, Indranil Sengupta: Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator. IEEE Trans. Computers 50(2): 177-185 (2001)
15		Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta: Theory and application of non-group cellular automata for message authentication. Journal of Systems Architecture 47(5): 383-404 (2001)
	2000
14		Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta: An ASIC for Cellular Automata Based Message Authentication. VLSI Design 2000: 538-
13		Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta: Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits. VLSI Design 2000: 544-549
	1998
12		Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri: Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. Asian Test Symposium 1998: 388-
11		Santanu Chattopadhyay, Parimal Pal Chaudhuri: Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis. VLSI Design 1998: 522-527
10		Santanu Chattopadhyay, Parimal Pal Chaudhuri: Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence. VLSI Design 1998: 564-
9		Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri: Cellular-Automata-Array-Based Diagnosis of Board Level Faults. IEEE Trans. Computers 47(8): 817-828 (1998)
	1997
8		Santanu Chattopadhyay, Parimal Pal Chaudhuri: Parallel Decoder for Cellular Automata Based Byte Error Correcting Code. VLSI Design 1997: 527-528
7		Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri: KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 257-265 (1997)
	1996
6		Santanu Chattopadhyay, S. Mitra, Parimal Pal Chaudhuri: Cellular automata based architecture of a database query processor. VLSI Design 1996: 320-321
5		S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri: Programmable cellular automata based testbed for fault diagnosis in VLSI circuits. VLSI Design 1996: 61-64
4		Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri: Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach. IEEE Trans. Computers 45(4): 487-490 (1996)
3		Koppolu Sasidhar, Santanu Chattopadhyay, Parimal Pal Chaudhuri: CAA Decoder for Cellular Automata Based Byte Error Correcting Code. IEEE Trans. Computers 45(9): 1003-1016 (1996)
	1995
2		Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri: Board level fault diagnosis using cellular automata array. VLSI Design 1995: 343-348
1		Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri: Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. VLSI Design 1995: 57-62

Coauthor Index

1	Debabrata Bagchi	[17]
2	Subarna Bhattacharjee	[2] [9]
3	Mayur Bubna	[36]
4	Mrityunjoy Chakraborty	[35]
5	Parimal Pal Chaudhuri	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [16]
6	Saurabh Chaudhury	[27] [38]
7	Naveen Choudhary	[20]
8	Dipanwita Roy Chowdhury	[2] [9] [17]
9	Batsayan Das	[23]
10	Prabir Dasgupta	[13] [14] [15] [16]
11	Manas Kumar Dewangan	[25]
12	Chandan Giri	[28] [29] [30] [31] [32]
13	Shantanu Gupta	[26]
14	M. Tilak Kumar	[33]
15	Santanu Kundu	[37]
16	Tapas K. Maiti	[34]
17	S. Mitra	[6]
18	Joy Mukherjee	[17]
19	Prasanta Kumar Nandi	[12]
20	S. Nandi	[5]
21	Ajit Pal	[39]
22	Rohit Pandey	[19]
23	Kolin Paul	[12]
24	Sambhu Nath Pradhan	[33]
25	M. Deb Purkayastha	[12]
26	B. Mallikarjuna Rao	[31]
27	J. Srinivasa Rao	[27]
28	K. Sudarsana Reddy	[21]
29	A. Roy	[12]
30	B. N. Roy	[12]
31	Samir Roy	[1] [4] [7]
32	Dipankar Sarkar	[23]
33	Soumojit Sarkar	[28] [30]
34	Jakki Sasidhar	[22]
35	Koppolu Sasidhar	[3]
36	D. Satyanarayana	[22]
37	Indranil Sengupta	[13] [14] [15] [16]
38	Rafiahamed Shaik	[35]
39	Naresh Shenoy	[36]
40	Krishna Teja Sistla	[38]
41	Dilip Kumar Reddy Tipparthi	[32]
42	Tarang Vaish	[26]

Colors in the list of coauthors