| 2009 | ||
|---|---|---|
| 34 | Gregory Lucas, Scott Cromar, Deming Chen: FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization. ASP-DAC 2009: 61-66 | |
| 33 | Scott Cromar, Jaeho Lee, Deming Chen: FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. DAC 2009: 838-843 | |
| 32 | Chen Dong, Scott Chilstedt, Deming Chen: Reconfigurable circuit design with nanomaterials. DATE 2009: 442-447 | |
| 31 | Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger: CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122 | |
| 30 | Chen Dong, Scott Chilstedt, Deming Chen: FPCNA: a field programmable carbon nanotube array. FPGA 2009: 161-170 | |
| 29 | Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles: Blueshift: Designing processors for timing speculation from the ground up. HPCA 2009: 213-224 | |
| 28 | Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu: High-performance CUDA kernel execution on FPGAs. ICS 2009: 515-516 | |
| 27 | Quang Dinh, Deming Chen, Martin D. F. Wong: A routing approach to reduce glitches in low power FPGAs. ISPD 2009: 99-106 | |
| 26 | Deming Chen: Design Automation for Microelectronics. Handbook of Automation 2009: 653-670 | |
| 2008 | ||
| 25 | Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, Deming Chen: VEBoC: Variation and error-aware design for billions of devices on a chip. ASP-DAC 2008: 803-808 | |
| 24 | Quang Dinh, Deming Chen, Martin D. F. Wong: Efficient ASIP design for configurable processors with fine-grained resource sharing. FPGA 2008: 99-106 | |
| 23 | Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu: Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor. SASP 2008: 20-25 | |
| 22 | Lei Cheng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) | |
| 21 | Lei Cheng, Deming Chen, Martin D. F. Wong: DDBDD: Delay-Driven BDD Synthesis for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1203-1213 (2008) | |
| 2007 | ||
| 20 | Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang: High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC 2007: 529-534 | |
| 19 | Lei Cheng, Deming Chen, Martin D. F. Wong: GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. DAC 2007: 318-323 | |
| 18 | Lei Cheng, Deming Chen, Martin D. F. Wong: DDBDD: Delay-Driven BDD Synthesis for FPGAs. DAC 2007: 910-915 | |
| 17 | Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig: Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. ICCAD 2007: 370-375 | |
| 16 | Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang: Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture. ICCAD 2007: 758-764 | |
| 2006 | ||
| 15 | Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. DAC 2006: 117-120 | |
| 14 | Joey Y. Lin, Deming Chen, Jason Cong: Optimal simultaneous mapping and clustering for FPGA delay optimization. DAC 2006: 472-477 | |
| 13 | Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu: Optimality study of resource binding with multi-Vdds. DAC 2006: 580-585 | |
| 12 | Deming Chen, Jason Cong, Junjuan Xu: Optimal simultaneous module and multivoltage assignment for low power. ACM Trans. Design Autom. Electr. Syst. 11(2): 362-386 (2006) | |
| 11 | Deming Chen, Jason Cong, Peichen Pan: FPGA Design Automation: A Survey. Foundations and Trends in Electronic Design Automation 1(3): (2006) | |
| 2005 | ||
| 10 | Deming Chen, Jason Cong, Junjuan Xu: Optimal module and voltage assignment for low-power. ASP-DAC 2005: 850-855 | |
| 9 | Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong: Power modeling and characteristics of field programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1712-1724 (2005) | |
| 2004 | ||
| 8 | Deming Chen, Jason Cong: Register binding and port assignment for multiplexer optimization. ASP-DAC 2004: 68-73 | |
| 7 | Deming Chen, Jason Cong, Fei Li, Lei He: Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA 2004: 109-117 | |
| 6 | Deming Chen, Jason Cong: DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. ICCAD 2004: 752-759 | |
| 5 | Deming Chen, Jason Cong: Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. ISLPED 2004: 70-73 | |
| 2003 | ||
| 4 | Fei Li, Deming Chen, Lei He, Jason Cong: Architecture evaluation for power-efficient FPGAs. FPGA 2003: 175-184 | |
| 3 | Deming Chen, Jason Cong, Yiping Fan: Low-power high-level synthesis for FPGA architectures. ISLPED 2003: 134-139 | |
| 2 | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1424-1431 (2003) | |
| 2001 | ||
| 1 | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. FPGA 2001: 39-47 | |